Leverage Hardware Acceleration for Faster Simulation

Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.

Today’s SoC design incorporates multiple third-party IP, embedded processors, and high-speed serial interfaces prolonging the test cycle since multiple modes of operation have to be tested. Traditional RTL simulation utilizing constructs such as testbenches, assertions, and output display message are bottlenecked by the simulator, which can lead to long simulation runs.  Verification and discovery of bugs can only be accomplished after the simulation has ended – which in turns reduces of the number of tests that can be implemented, which can result in re-spins of the final ASIC.

Hardware-assisted verification utilizing FPGA-prototyping boards for designs up to 96 million ASIC gates eliminates the major verification hurdles of traditional simulation. In acceleration, synthesizable portions of the DUT are mapped to the FPGA, and evaluated in parallel with HDL constructs in the simulator. This is facilitated via high-speed physical channel utilizing PCIe interface connecting both the FPGA board and the PC.

Aldec provides an automated and fully scriptable environment, HES Design Verification Manager (HES-DVM™), which takes designers from RTL source files to FPGA bit files. Users can also setup debugging probes for visibility in the DUT, which can be observed in Aldec or third-party waveform viewers. In addition, HES-DVM also has a rich set of features such as: memory mapping, automatic/guided partitioning, memory peaking/poking via gui or API, EDIF support, and many more.

On Thursday, August 8, 2013, I will host a webinar which will run through some of the verification problems that co-simulation solves, and also present how HES-DVM integrates with Aldec’s functional verification platform, Riviera-PRO™. A sample design will be presented showing design setup in HES-DVM, as well as debugging from within the waveform viewer of the hardware implementation. Visit www.aldec.com/events to register for this upcoming webinar, Accelerate SoC Simulation Time of Newer Generation FPGAs.

Tags: acceleration, Aldec, asic gates, FPGA, fpga boards, fpga-based prototyping boards, hardware acceleration, Hardware Emulation, HDL, hdl simulation, hes design verification manager, HES-DVM, Riviera-PRO, rtl simulator, soc design, system-on-chip verification cycle

Category: Emulation/Acceleration

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