Posts Tagged ‘Aldec’
Wednesday, November 9th, 2016
 As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich – the city of pork knuckles, beer… and of course, cars.
 The DVCon Europe conference is certainly growing, and the methodology presented yearly continues to be more mature and ready to use. This year’s DVCon Europe was not thematically different from other conferences. Subjects like Automotive and IoT have flourished these past few years.
Yet, nowhere else like here in the heart of Bavaria has the discussion about cars acquired such importance. In this region known as the European Detroit, cars are a secular religion.
A few years ago we were wondering… how? Two years ago… when? Today production has its hands full and engineers are simply wondering… what’s next?
As with the American election, there is a sense that we are awaiting another revolution. Within a few dozen years, internal combustion engines will become extinct like dinosaurs, or become as Juergen Weyer of NXP has said, like “Kodak in the era of digital photography”.
And so we turn to the electronics field as the main solution for this new era. With this turn, ahead of us opens up new challenges related to design and testing, not to mention the safety of billions of users.
In the vastness of topics such as Automotive and IoT, I would not want us to miss this nugget from this year’s DVCon Europe Conference: UVVM, VHDL’s long-awaited alternative to UVM. With the large presence of VHDL in Europe, Universal VHDL Verification Methodology (UVVM) could not have been born anywhere else. The concept is based on the Bus Functional Model enriched by the favor of the well-known and liked OSVVM… and it promises to be interesting.
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Tags: Active-HDL, Aldec, bus functional model, dvcon, fpga vhdl verification, uvvm, vhdl europe
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Wednesday, August 17th, 2016
Today’s article is authored by Zach Nelson, Aldec FAE Intern. Zach is a Field Application Engineer Intern with Aldec, working in tandem with his fellow interns to develop hardware specific applications. He is set to graduate with a B.S. in Electrical Engineering from University of Nevada, Las Vegas in 2017. His field interests include ASIC Design & Solid State Electronics.
It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities.
What can Zynq do?
The Zynq chip has applications in the design fields related to:
- FPGA
- Digital Design
- VHDL/Verilog
- Embedded Systems
- Robotics
- IoT
- Factory Automation
- Algorithm Implementations
- Signal Processing
- Video/Image Processing
FPGA
The Programmable-Logic can be used in isolation of the processor which allows it to be used like a general FPGA device which can help support the topics covered in any VHDL/Verilog class as well as Digital Design. It is much easier to facilitate growth and learning in a project-based curiculum when you have a device such as the Zynq to interface with.
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Tags: Active-HDL, Aldec, embedded, FPGA, Xilinx, Zynq
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Wednesday, August 17th, 2016
 Today’s article is authored by Brandon Wade, Aldec FAE Intern. Brandon is currently working on his B.S. in computer engineering from the University of Nevada, Las Vegas and is set to graduate in 2017. His interests include processor architectures, and the logic of these hardware designs. As a field application engineer intern, Brandon has worked extensively with Aldec’s own simulation software such as Active-HDL and Riviera-PRO.
When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you are addressing. The same is necessary with electronics, especially with system on chip (SoC) designs.
The protocol used by many SoC today is AXI, or Advanced eXtensible Interface, and is part of the ARM Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx’s Zynq devices, providing the interface between the processing system and programmable logic sections of the chip.
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Tags: Aldec, ARM, embedded, TySOM
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Friday, December 4th, 2015
 Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.
So what is UVM?
UVM stands for universal verification methodology and is based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.
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Tags: Aldec, Riviera-PRO, uvm, verification
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Tuesday, August 25th, 2015
 You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your mind. You are confident that your designs are fault-tolerant and will function as intended. You are the master of your domain.
But… can you bet your life on it?
Are you willing to bet your life on your designs? What about the lives of the thousands of passengers sitting on the airplanes where your FPGA design is installed? How certain are you that it won’t fail in the field? If it were to fail, can it resume normal operation safely and timely? Not just MOST of the time, but EVERY time?
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Tags: Aldec, do-254, DO-254 Compliance, do-254/cts, FPGA Design, FPGAs, Requirements Management, safety-critical, spec-tracer, Traceability
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Monday, April 20th, 2015
How to use VIPs In Practice
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.
Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.
Figure 1. Typical verification process
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Tags: Aldec, Emulation, HES-7, HES-DVM, ICE, In-circuit emulation, Kamil Rymarz, Monitor, Riviera-PRO, SoC Verification, Speed Adapter, Test, Transactor, Validation, Verification IP
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Tuesday, February 24th, 2015
 Taking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment.
All Tcl scripts contributed to the Xilinx repository are free and re-distributable under an open-source license that is based on the Berkeley Source Distribution (BSD) model. Vivado users can now download apps from the Tcl Store that include practical bundles of Tcl scripts that act just like Vivado commands, including an app that can integrate Aldec Active-HDL and Riviera-PRO tools within the Vivado design flow.
To take advantage of these pre-packaged Tcl Script apps within Vivado, users can access the Tcl Store via the Vivado IDE “Tools” menu. For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Active-HDL Simulator, Aldec, Aldec Active-HDL, Riviera-PRO tools, Tcl scripts, Tcl Store, Vivado design flow, Vivado Integrated Design Environment, Xilinx
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Tuesday, February 24th, 2015
This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning math, science, and technical skills.
I work with Generation STEAM, a group organized by the SYN Shop MakerSpace and the Henderson district library to create a series of STEM (Science, Technology, Engineering, [Art], and Math) classes that are free to the public. For my part, I’ve had the privilege of teaching a basic electronics class for kids a few Saturdays this year – and it’s been a blast. Our hope is that we are encouraging a few young people to follow the path of engineering.
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Tags: Aldec, Electronics Engineering, engineers week, future engineers, SoC and ASIC Prototyping, STEM
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Wednesday, January 21st, 2015
 Happy New Year!
January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.
The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).
Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.
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Tags: Active-HDL, Aldec, Digital Design Verification, FPGA hardware platform, HES-DVM, International CES, internet of things, millions of ASIC gates, Multiple HES-7 FPGA development boards, Riviera-PRO, SoC and ASIC Prototyping, Xilinx Virtex-7
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Wednesday, December 10th, 2014
 In response to user feedback, Aldec has developed a direct integration between IBM® Rational ® DOORS ® and our requirements management tool, Spec-TRACER™, to enable users to extend the traceability data in DOORS to FPGA design and verification elements.
Aldec has a strong 30-year+ history of asking and listening to the engineering community and we’re proud to say, thanks to your requests, that Spec-TRACER 2014.12 featuring direct integration with DOORS… is now available to test drive.
Below you’ll find an overview of the Spec-TRACER/DOORS tool flow. DOORS remains the main source and environment for managing board requirements and other higher level requirements, while Spec-TRACER remains the main source and environment for managing FPGA requirements, conceptual design data, detailed design data, test cases, test procedures, test results, traceability data and review activities. Spec-TRACER also remains the main source for generating all the pertinent reports for the FPGA project such as requirements documents, verification procedures, test results, impact analysis reports and project status reports.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, conceptual design data, detailed design data, environment for managing fpga requirements, FPGA Design, fpga project, ibm rational doors, impact analysis reports, managing board requirements, managing higher level requirements, project status reports, requirements documents, review activities, spec-tracer, test cases, test procedures, test results, traceability data, verification elements, verification procedures
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As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich – the city of pork knuckles, beer… and of course, cars.
