Search Results
Monday, November 25th, 2013
Tags: agilent, Aldec, co-simulation, co-simulation flow, co-simulation solution, comrate, debugging, digital blocks, hdl models, mixed-signal, model-based design, multirate design, Riviera-PRO, system-level environment, system-level simulation, systemvue, verification, verification of multirate systems with multiple digital blocks
No Comments »
Wednesday, November 20th, 2013
Tags: Aldec, arinc 818, arinc protocol for high bandwidth, aviation, avionics systems, c/c++ api, do-254, do-254/cts, FPGA, fpga designs, in-hardware verification results, low latency, mil/aero verification solution, safety-critical, uncompressed digital video transmission, waveform
No Comments »
Wednesday, November 6th, 2013
Tags: Aldec, ARM, arm processors, arm techcon conference, arm-based processors, co-simulation, dual-core arm cortex-A9 processors, Emulation, hes-7 platforms, hes-7 soc db, HES-DVM, hw/sw verification platform, ICE, In-circuit emulation, prototyping, rtl simulation, SoC, SoC and ASIC Prototyping, Xilinx, xilinx zynq soc
No Comments »
Wednesday, October 9th, 2013
Tags: accelera, Aldec, Emulation, function-based infrastructure, HES-DVM, macro-based sce-miI, sce-mi macro-based infrastructures, SoC, soc design verification time, systemc, systemverilog, systemverilog dpi functionality, verification
No Comments »
Tuesday, September 24th, 2013
Tags: Aldec, coverage, fifo test, functional coverage holes, intelligent coverage, os-vvm, osvvm-style constrained random, randomization, systemverilog, VHDL, vhdl testbench techniques
No Comments »
Monday, September 23rd, 2013
Tags: Aldec, cca, circuit card assembly, conceptual design, detailed design, do-254, FPGA, fpga requirements, hardware design process, hardware requirements, HDL Design, implementation, individual system requirements, requirements capture, spec-tracer, test results, Traceability, verification results, verification test cases
No Comments »
Wednesday, September 18th, 2013
Tags: accelera, Aldec, co-simulation, dpi, Emulation, FPGA, function-based, hardware, hardware emulation platform, hardware-assisted verification method, hardware-assisted verification solution, hdl simulations, high-level testbenches, macro-based, pipes-based, prototyping, rtl simulator, sce-mi, simulation acceleration, SoC, SoC and ASIC Prototyping, soc designs, standard for co-emulation modeling interface, system-on-chip verification, systemverilog direct programming interface, systemverilog lrm, transaction-level co-emulation, transaction-level co-emulation methodology, Validation, verification
No Comments »
Monday, September 16th, 2013
Tags: Aldec, analog, co-simulation, digital, hiper simulation a/ms, mixed-level simulation, mixed-signal, mixed-signal design approach, Riviera-PRO, safety-critical, simulation-based verification, tanner eda, transistor-level implementation, verilog-ams simulators, vhdl languages
7 Comments »
Monday, September 9th, 2013
Tags: Aldec, clocks, design, hand-coded rtl, hardware design flow, hierarchies, high level synthesis, hls tool, processes, rtl, SoC, SoC and ASIC Prototyping, systemc, technology, Validation, verification
No Comments »
Wednesday, August 28th, 2013
Tags: Active-HDL, Aldec, assertions, cen, chinese electronics news, co-simulation, coverage, debugging, debugging tools, design, digital, documentation, FPGA, fpga design simulation solution, fpga designs, HDL, ieee, matlab, os-vvm, project management, semiconductor industry, simulation, simulation platform, standards, top fpga design, university, verification, verification platform, verilog, VHDL, Xilinx
No Comments »
|
