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Wednesday, July 16th, 2014
Tags: aviation, coverage, design, do-254, DO-254 Guidance, FPGA, HDL Design, Impact Analysis, Requirements-Based Verification, safety-critical, Testbench, Traceability, Validation, verification
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Tuesday, June 24th, 2014
Tags: Aldec, design, do-254 project, do-254/cts, easa verification audit for do-254/ed-80 dal a fpgas, elbit systems aerospace division, elbit systems in Israel, FPGA, fpga at-speed testing, fpga physical testing platform, fpga pin-level requirements, logic design verification group leader, simulation, simulation testbench, software test vectors, test vectors, Traceability, verification
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Tuesday, June 24th, 2014
Tags: Aldec, aldec 30th anniverssary, aldec 30th birthday party, dac 2014, dac chat, embedded, gopro hero3+ camera, Hardware Emulation, safety-critical, SoC and ASIC Prototyping, training, uvm, uvm methodologies, verification, vhdl verification using osvvm
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Thursday, May 15th, 2014
Tags: advanced vhdl testbenches, Aldec, bist, built-in self test, coverage, design, design and verify programmable devices, finite-state machine, FPGA, fpga design engineers, fsm, functional coverage, ieee 1076 working group chair, ieee 1149.1 tap, open source vhdl verification methodology, os-vvm chief architect, osvvm, random value generation, randomization, test access port controller, test mode select signal, testbench development, tms signal, verification, verification packages, verification training course, verification with vhdl, VHDL, vhdl 2008 features, vhdl osvvm CoveragePkg to a fsm
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Wednesday, April 9th, 2014
Tags: Aldec, conceptual design, design, do-254, FPGA, FPGA Design, fpga requirements, HDL Design, ibm doors, Impact Analysis, impact analysis defined, log files, post-layout design, requirements-based test cases, simulation runs, spec-tracer requirements lifecycle management solution, Testbench, Traceability, verification, waveforms
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Thursday, March 13th, 2014
Tags: advanced verification platform, Aldec, hdl code, image plots, plot feature, plot windows, polar, qam constellations, resources, Riviera-PRO, simulation, time-domain based results analysis, traditional waveforms, using plots for hdl debugging, vector, verification
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Thursday, February 20th, 2014
Tags: Aldec, capture requirements, develop test cases, develop testbench, device testing with do-254/cts, do-254, final board testing, FPGA, fpga device, functional simulation code coverage, increase verification coverage by test, simulation, simulation models, test vectors for device testing, timing simulation, verification, verification methods
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Tuesday, January 21st, 2014
Tags: Aldec, cca, circuit card assembly requirements, do-254, DO-254 Compliance, FPGA, FPGA Design, HDL Design, higher level requirements, ibm doors, line replaceable unit, lru, managing fpga requirements, spec-tracer, Traceability, traceability with excel, verification elements
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Friday, January 10th, 2014
Tags: Active-HDL, aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
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