Posts Tagged ‘Synopsys’
Thursday, March 21st, 2013
It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.
 Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.
In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.
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Tags: ARM Connected Community, Cadence, DAC 2013, DAC Exhibit Hall, DAC Innovation Square, GlobalFoundries, Synopsys, TSMC
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Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
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Tags: 14nm FinFET, Aart de Geus, Ansys, Apple, ARM, Cadence, Computer History Museum, DAC, DATE, DoubleTree, EDA Reunion, EUV, Google, Gordon Moore, Jasper Design Automation, Jim Hogan, Joe Costello, Kathryn Kranen, Lip-bu Tan, Mentor Graphics, MOD Marketing, Nimbic, OCP-IP, Raul Camposano, Rich Valera, Samsung, Simon Segars, Synopsys, Wally Rhines
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Thursday, March 7th, 2013
If you were lucky enough to be at the ISQED Poster Session in Silicon Valley on Tuesday afternoon, March 5th, you had a chance to speak with various university students presenting novel work, various industry researchers presenting new ideas, and Chi-Foon Chan, Co-CEO of Synopsys, whose long involvement with ISQED, and deep and abiding interest in the underlying technology, fueled lively conversations as he too visited posters being presented by academia and industry alike.
As well, you would have had a chance to speak with Prof. Daniela De Venuto from the Politecnico di Bari. She told me about her research into implanted devices which monitor rate of chemical absorption in the digestive tract, and ways in which the resulting data could impact our understanding of the biochemistry of drug delivery mechanisms.
She also told me about various fascinating sessions at the upcoming DATE 2013 conference in Grenoble, starting on March 18th. These sessions are of particular merit for anyone interested in the interface between biological systems, electronic systems, environmental systems, and all manner of collaborative research embracing them all.
On March 21st, Prof. De Venuto is chairing a session on Smart Health along with U.C. Berkeley Prof. Alberto Sangiovanni-Vincentelli. The session is part of a Special Day on Electronic Technologies for Smart Cities.
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Tags: Alberto Sangiovanni-Vincentelli, Chi-Foon Chan, Daniela De Venuto, DATE 2013, EPFL, Imec, ISQED 2013, Politecnico di Bari, Synopsys, U.C. Berkeley
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Thursday, February 21st, 2013
You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.
If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.
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Tags: Accellera Systems Initiative, Cadence, DVCon 2013, Free Lunch, Harry Foster, John Brennan, Mentor Graphics, Synopsys, Wilson Research Group Functional Verification Study, Yatin Trivedi
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Wednesday, January 16th, 2013
There are three reasons why DAC will be spectacular come June in Austin: It’s the 50th instantiation of the conference; for the first time ever DAC is coming to the home of Office Space; and Synopsys Solutions Group Chief Architect Yervant Zorian will be General Chair, which means the 2013 Design Automation Conference has got the very best in the business at the top, a guy who’s CV includes leading committees of all shapes and sizes, IEEE Standards initiatives, and a variety of conferences, big and small.
Zorian’s track record in the industry is well known. My own article, Yervant Zorian: Grand Master of Time Management, was published on the DAC website in 2007. But all that said, it’s a personal recollection of Yervant Zorian that I prefer.
In 1999, I was tasked with writing my first Focus Report for ISD Magazine, a now-defunct publication of Miller Freeman CMP UBM, on the subject of DFT, Design for Test. Tets Maniwa was Editor in Chief of the magazine at the time and he suggested that I call Yervant Zorian for some technical background on DFT, BIST, and all that jazz.
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Tags: DAC 2013, Design Automation Conference, ISD Magazine, Logic Vision, Synopsys, Tets Maniwa, Virage Logic, Yervant Zorian
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Thursday, December 6th, 2012
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
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Tags: Altera, ARM TechCon, Blue Pearl, DATE, DesignCon, Grey Cell Methodology, RTL Signoff for FPGAs, SAME, Shakeel Jeeawoody, SNUG, Synopsys, Synplicity, Xilinx
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Monday, November 12th, 2012
If you’re an IP developer, or somebody who develops SoCs where blocks of IP land, Synopsys is announcing a product today that will be of interest: the HAPS-70 Series. It’s a prototyping system with a distinguished provenance that runs your ASIC-targeted design on FPGAs for validation prior to tape-out.
HAPS-70 started its journey to your work place way back in 1987 when Sweden-based HARDI Electronics was founded. The folks at HARDI developed the original HAPS prototyping system, which became part of Synplicity’s arsenal in 2007 when HARDI was acquired by SYNP, and the product was relaunched as HAPS-54.
Gary Meyers was President and CEO of Synplicity at the time, and was quoted: “This is a major strategic move for Synplicity. We will be able to immediately leverage our existing ASIC verification products (Certify, Synplify Premier, Identify, and Identify Pro) by selling them together with the HARDI ASIC prototyping boards.”
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Tags: ASIC prototyping, FPGA-based prototyping, Gary Meyers, HAPS, HARDI Electronics, Mentor Graphics, Mick Posner, Neil Songcuan, Synopsys, Synplicity
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Thursday, November 8th, 2012
It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.
 Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”
He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”
All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.
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Tags: ASML, Ausdia, Avanti, Brion Technology, Cadence, CadMOS, Cronox Group, Epic Design, Extreme DA, Frequency Technology, Frontline Design Automation, Mentor Graphics, Mobi-holdings, Plato Design, Q Design, Sanjay Lall, Sente, Silicon Software, Summit Design, Synopsys, Triquest, Ultima Interconnect, Verdigirs Technologies
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Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
 In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”
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Tags: Cadence, Celestry Design, DFY, IBM, Mentor Graphics, Monte Carlo, NanoYield, ProPlus, ProPlus Design Solutions, statistical variation, Synopsys, TSMC, Zhihong Liu
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Thursday, October 25th, 2012
Montreal is not a place that normally comes to mind when you think of EDA. Space Codesign Systems, however, is on a fast track to change that in a classically Canadian way – calm, cool, and collected.
When I spoke with General Manager Dr. Gary Dare on a beautiful afternoon in Southern France at SAME Forum in early October, he explained how the company started in Canada, and the road map they have set out for themselves: “We’re an EDA company, an EDA startup, and we are definitely based in Montreal. If you doubt that EDA has a place in Canada, we will soon convince you otherwise.
“Space Codesign comes from the acronym, SystemC Partition of ACE, which was the 2004 research project at the Ecole Polytechnique [University of Montreal] that our technology is based on. In 2008, Professor Guy Bois and various graduate students associated with the project decided to do a spin-out, and in 2010 Space Codesign Systems went into operation.”
He laughed and added, “Our company has nothing to do with space, however. But it has everything to do with hardware/software co-design – doing it simultaneously, rather than the usual way of ESL hardware design followed by software design. The audience we are targeting is the systems architects who are looking at the algorithmic level and need a route to design exploration and implementation. Our tools give them that route.
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Tags: ARM Connected Community, ASIC, C/C++, Calypto, Canadian VCs, CoWare, ESL, Forte, FPGA, Gary Dare, Global Foundries, Guy Bois, hardware/software codesign, MATLAB, Mentor Graphics, Montreal, NoC, Space Codesign Systems, Synopsys, SystemC, TSMC, UML, University of Montreal, Vista
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Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.
