What Would Joe Do?
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
DVCon 2013: There is such a thing as a free lunch!
February 21st, 2013 by Peggy Aycinena
You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.
If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.
On Monday, industry legend Yatin Trivedi will host the Accellera Systems Initiative event, billed as a “Town Hall style” discussion of current challenges for the design community, including “developing standards-by-committee and deploying standards in active projects” using SystemC, SystemVerilog, Verilog-AMS and IP-XACT.
On Tuesday, the equally legendary Harry Foster will host Mentor Graphics’ event where the agenda is centered around “the first public release of highlights from this year’s Wilson Research Group Functional Verification Study.” Now come’on, does it get any better than that? And free lunch?
On Wednesday, industry expert John Brennan will host Cadence’s contribution to the DVCon mid-day culinary classroom: “Best Practices in Verification Planning”. The hour will include a panel discussion with Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan.
These guys are promising to have “an open discussion about what’s working and what’s not — covering topics from methodology to human factors to automation techniques known to provide proven results.” Overplanning, tracking, merging, and keeping bugs from going rouge? You better be there to see if this group can make good on their promise of constructive solutions to your problems.
Finally, Thursday offers a chance for Synopsys to serve up a “highly informative session that will cover the latest verification trends, challenges and solutions. Synopsys and leading industry experts will share their viewpoints on what is driving SoC complexity, introduction to Synopsys’ next-generation Verification IP architecture, and user perspectives on verification IP, UVM, and other topics.” Among those topics is the free lunch. The rest of the hour will be pure icing on the cake, so don’t miss it.