Posts Tagged ‘Qualcomm’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
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Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
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Thursday, August 31st, 2017
Amit Gupta is the quintessential entrepreneur in EDA. Even as he was graduating with degrees in EE and CS from University of Saskatchewan, he was co-founding Analog Design Automation, targeted at those who need tools to automate analog chip design. That was in 1999. The company was sold to Synopsys in 2004, and then Gupta co-founded Solido Design Automation in 2005.
This week, I had a chance to speak at length with Amit Gupta. The last time we conversed, it was at the January 2017 Kaufman Award dinner for Dr. Andres Strojwas in San Jose. That evening, Gupta was enthused about Solido’s access to high-quality engineering talent in Canada, and argued that the cost of living and quality of life in Saskatoon, where Solido is headquartered, more than compensate for any sense that Silicon Valley is the epicenter of the industry. His enthusiasm has only grown since that time.
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Tags: Amit Gupta, Analog Design Automation, Deloitte, Design Automation Conference, E3 Data Science, Eric Hall, ESD Alliance, finFET, GlobalFoundries, Gloria Nichols, Jeff Dyck, Mark Gilbert, NVIDIA, Qualcomm, Samsung, Saskatoon, SOI, Solido Design Automation, Sorin Dobre, Synopsys, Ting Ku, TSMC, UX design
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Thursday, February 23rd, 2017
Accellera has just announced that Lu Dai, Senior Director of Engineering at Qualcomm, is the new chair of the organization.
Although Intel’s Shishpal Rawat, recently retired from Intel, is a hard act to follow as Accellera Chair given his long, productive years leading the organization, if anyone can do it Lu Dai can. He’s enthusiastic, energetic, optimistic, and an engineer – and not necessarily in that order.
Before talking about Accellera in our phone call this week, Dai spoke about DVCon, anchor tenant of Accellera’s outreach to design and verification engineers around the world. This next week, the Silicon Valley version will unfold in San Jose, with DVCon India happening in September, DVCon Europe in October, and the first-ever DVCon China in April.
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Tags: Accellera, DVCon, DVCon China, DVCon Europe, DVCon India, DVCon U.S., Lu Dai, Qualcomm, Shishpal Rawat
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Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
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Tags: Accellera, Accellera PSWG, Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, DVCon, Faris Khundakjie, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Portable Stimulus Working Group, Qualcomm, Semifore, Synopsys, Tom Anderson, Tom Fitzpatrick, Vayavya Labs
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Thursday, January 23rd, 2014
Long, long ago in a galaxy far, far away the EDA Empire began and quickly coalesced into several big players and a band of plucky startups constantly attempting to compete and stay viable.
Back in that halcyon era, Rick Carlson and Dave Millman decided to get those startups to pull as one, to try to keep the industry open and progressing, to protect the EDA industry as a place where new ideas could see the light of day and offerings from small companies could compete on a level playing field against those from the big players.
To do that, Rick and Dave came up with the idea for a consortium of Independent Design Automation Companies, IDAC, and put out the word to like-minded colleagues that this new group would benefit everybody. Creating IDAC proved more difficult than they had hoped, so letting pragmatism rule the day they approached Joe Costello for help, then CEO of Cadence, even though that meant working with one of the ‘big guys’ and hence, EDAC came to fruition.
To hear the rest of the story per Rick, recounted in a phone call in December, click here.
To hear the story recounted by Joe Costello, read below. I spoke with both Joe and Rick together on a conference call in mid-January.
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Revolution from within …
Joe began: “Rick told me he’s concerned that in his recent conversation with you about the history of EDAC, he may have sounded too harsh. I said that’s not possible, because the truth about the industry is quite harsh. Just thinking about it makes my blood boil.
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Tags: all-you-can-eat EDA, Broadcom, Cadence, Dave Millman, EDAC, EDAC Interoperability Lab, IDAC, Intel, Joe Costello, Mentor Graphics, Qualcomm, Rick Carlson, Samsung, Synopsys
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