Posts Tagged ‘ESL’
Tuesday, December 2nd, 2014
This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from being a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.
To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.
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Tags: Breker, coverage, EDA, equivalence checking, ESL, formal analysis, functional verification, HDL, high-level synthesis, HLS, portable stimulus, reuse, RTL, scenario model, Verilog
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Thursday, October 16th, 2014
I spent Tuesday of this week in the Winchester Mystery House, San Jose’s best-known tourist attraction, hearing a wide variety of opinions about design IP, verification IP (VIP), the Internet of Things (IoT), and related topics. “Unlock the Mystery of IP: Silicon Valley IP Users Conference” was organized and presented by IPextreme and their Constellations program partners. I found most of the talks quite interesting, and would like to share some thoughts on what the experts’ projections might mean for Breker and our customers.
There is no doubt that the increasing use of IP is key to designing ever larger chips. Kands Manickam of IPextreme noted that, over the next five years, the compound annual growth rate (CAGR) of IP blocks and subsystems is expected to be 12% versus 3.5% for semiconductors. Randy Smith of Sonics reported that the average large chip today has about 120 blocks, growing to more than 200 by 2018. We already know that VIP reuse is not as effective as design IP reuse, and these projections will only exacerbate the gap.
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Tags: Accellera, Breker, DV, ESL, functional verification, IoT, IP, IPextreme, portable stimulus, SoC, SoC verification, uvm, VIP
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Wednesday, October 8th, 2014
Last week we summarized some of the activities at the inaugural DVCon India. Breker was not the only company impressed by this show. For example, CVC wrote two posts on their VerifNews blog describing the excitement and range of technical content at the show. Gaurav Jalan captured several aspects of the show in his Sid’dha-karana blog, focusing specifically on the keynote speakers. The Agnisys blog also provided a nice overview. Clearly this was a very successful event.
The high quality of the technical content and the excellent attendance at DVCon lead me to think about how much India has changed in just a few years. I first had an engineering team there in 1995, nearly 20 years ago. I recall my first trip to India very well and the contrast with recent visits is tremendous. I’ve been deeply impressed by the evolution of electronics development in India and I see the DVCon success as both a tribute to where the community is today and a sign of even better things to come.
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Tags: Accellera, Bangalore, Breker, chennai, DV, dvcon, ESL, functional verification, India, madras, portable stimulus, SoC, SoC verification, uvm
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Friday, October 3rd, 2014
Over the last several blogs posts, we’ve twice previewed the very first DVCon India show, celebrating it as a sign of India’s ever-growing importance in the electronics industry. We also mentioned that our co-founder and CEO Adnan Hamid would be presenting in two tutorials and helping to staff our booth in the exhibition. Now that the event is over and Adnan has returned from his travels, we’d like to fill you in what turned out to be a great event.
We have heard nothing but positive comments from attendees, vendors, and organizers. The conference was well attended, full of strong technical content, and well run. Perhaps the dominant theme to emerge was the importance of the “portable stimulus” effort undertaken by Accellera and the solutions available to meet some or all of the vision. It may be a stretch to call DVCon India the “Portable Stimulus Conference” but surely the first day (Thursday) was “Portable Stimulus Day” and we’ll explain why.
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Tags: Accellera, Bangalore, Breker, Cadence, CVC, DV, dvcon, ESL, functional verification, India, mentor, portable stimulus, Synopsys, uvm
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Wednesday, September 17th, 2014
One of the many challenges faced by small software companies is evolving their product lines in ways that make sense. New products must mesh with existing products so that customers can quickly understand what they might want. Products must be differentiated enough to stand separately, yet should leverage some of the same technology and expertise. Small companies have limited resources and it’s usually a mistake to develop multiple unrelated products requiring separate engineering teams.
Breker is no exception; we have a bunch of smart people with lots of ideas about how graphs can be applied to a wide range of problems. However, by focusing on the functional verification of large, complex chips using graph-based scenario models we are able to target a fairly specific group of companies and users. We also get tremendous productivity from a small R&D team because their collective knowledge spans the limited but important product range that we cover. This blog post is an attempt to describe that range more precisely.
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Tags: applications, apps, Breker, coverage, EDA, ESL, functional verification, graph, portable stimulus, products, reuse, scenario model, SoC verification, software-driven verification, transactional, Trek, TrekSoC, TrekSoC-Si, TrekUVM, UVC, uvm
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Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
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Tags: Accellera, apps, ARM, austin, Bangalore, Boston, Breker, Cadence, coherency, CVC, DV, dvcon, ESL, functional verification, India, mentor, Newton, portable stimulus, Santa Clara, SNUG, Synopsys, TechCon, TrekSoC, TrekSoC-Si, TrekUVM, uvm
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Friday, August 29th, 2014
As anyone involved in chip development knows, one of the biggest events of the year is the Design and Verification Conference and Exhibition, DVCon, which has been held for many years in San Jose. I’ve frequently shared my thoughts on this show and its importance to the industry in this blog. In just four weeks, DVCon expands to Bangalore for the very first DVCon India show. The full program for September 25-26 is now online and I’d like to focus on a few highlights from my perspective.
The first thing to note is the breadth of material being covered. The technical track is split between electronic system level (ESL) and design and verification (DV) topics, with a slight edge to the latter in terms of overall sessions. There are as many as five tracks in parallel, which is quite an accomplishment for a brand-new event. I know that there were many excellent session proposals submitted, which means that those selected are likely to be of high quality and wide interest.
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Tags: Accellera, Bangalore, Breker, Cadence, CVC, DV, dvcon, ESL, functional verification, India, mentor, portable stimulus, Synopsys, uvm
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