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 The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

Preview of an Exciting New Show: DVCon India

August 29th, 2014 by Tom Anderson, VP of Marketing

As anyone involved in chip development knows, one of the biggest events of the year is the Design and Verification Conference and Exhibition, DVCon, which has been held for many years in San Jose. I’ve frequently shared my thoughts on this show and its importance to the industry in this blog. In just four weeks, DVCon expands to Bangalore for the very first DVCon India show. The full program for September 25-26 is now online and I’d like to focus on a few highlights from my perspective.

The first thing to note is the breadth of material being covered. The technical track is split between electronic system level (ESL) and design and verification (DV) topics, with a slight edge to the latter in terms of overall sessions. There are as many as five tracks in parallel, which is quite an accomplishment for a brand-new event. I know that there were many excellent session proposals submitted, which means that those selected are likely to be of high quality and wide interest.

Some of the keynotes are still being confirmed, a common occurrence for conferences trying to snag busy executives. But Mentor CEO Wally Rhines, TI MCU CTO Mahesh Mehendale, and Martin Vaupel from Robert Bosch make a great start. The ESL sessions cover most of the expected topics, including TLM, SystemC models, UML, IP-XACT, AMS, and high-level synthesis. There’s a nice mix of half-hour papers and longer, in-depth tutorials.

Not surprisingly, the DV tracks are the most exciting to me. The very first session offers a tough choice. Universal Verification Methodology (UVM) expert Doulos has a tutorial on “Easier UVM” that should draw a good crowd. But at the same time, the hot topic of portable stimulus will be covered by Breker, Mentor, and CVC. This is not an official status report from the Accellera Proposed Working Group but rather a discussion of the underlying need in the industry for portable tests.

Scanning through the paper sessions, I see a number that look especially worthwhile. There are several UVM-related topics, including system-level randomization, improving simulation performance, reusing sequences, and (again!) making UVM easier to use. I see a continuation of a recent trend as DVCon focuses more on analog and AMS design and verification. This is presumably a reflection of the increasing wireless connectivity for all manner of devices.

Formal and static analysis also get their due. Mentor has an interesting-sounding talk on model abstraction. There are a couple of talks on clock domain crossing (CDC) verification, an essential part of the project for an SoC than may have dozens of different clock domains. Likewise, a chip may have dozens of power domains and here are three talks on low-power design and power-aware verification.

As in the San Jose version, DVCon will include an exhibition as well as a technical conference. About 25 companies will show demos and present their products. There will also be ample opportunities to network with both vendors and fellow attendees. I attended a CDNLive event in India a few years ago, and was amazed at the level of excitement and enthusiasm. I have every expectation that DVCon India will be lively and stimulating as well.

Breker is supporting this event in several ways. I am honored to be serving on the Promotions Committee, and this post is one of multiple steps I will take to let people know about this show. We are co-sponsoring the portable stimulus tutorial I mentioned earlier, and our CEO Adnan Hamid will be presenting. Adnan will also be making a guest appearance at a debug tutorial co-sponsored by Synopsys and CVC, demonstrating our integration with the Synopsys Verdi debug solution.

If you’re doing design or verification in India, or you can possibly travel there, I highly recommend attending DVCon India. It’s certain to be educational and fun as well. Please be sure to attend our two tutorials if you can. Thanks, and we’ll see you in Bangalore.

Tom A.

The truth is out there … sometimes it’s in a blog.

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One Response to “Preview of an Exciting New Show: DVCon India”

  1. Vineet Kumar says:

    First of all, many congretulations,
    this year DVCON is happening in india by the last week of this month and I am realy excited to join this event and thank you for participating in this even by the breker, specially for your both of the tutorials regarding portable stimulas, I am using Trek(from BrekerSystems) a graphical based constraint solver for functional verification of complex designs from before last six months through CVC Bangalore. So this will be more helpful to extend my knowledge and experience.
    I hope all of you will take a good benifit by joining this event.

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