Archive for the ‘Uncategorized’ Category
Tuesday, December 17th, 2024
At the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled a series of pioneering advancements poised to reshape the semiconductor landscape for the coming decade. With innovations addressing transistor scaling, interconnect efficiency, and advanced packaging, Intel’s research highlights the company’s leadership in enabling the exponential growth of computing power required to meet artificial intelligence’s (AI) insatiable demands.
As AI continues to push the limits of existing technology, the need for energy-efficient, high-performance chips grows ever more critical. Intel’s latest breakthroughs mark significant steps in transistor miniaturization, interconnect materials, and assembly techniques—key ingredients for sustaining Moore’s Law and advancing toward a trillion-transistor chip by 2030.
“Our research at Intel Foundry is focused on overcoming the technological roadblocks of tomorrow,” said Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research. “These advancements reflect our mission to deliver cutting-edge semiconductor innovations, developed domestically, to meet global AI demands and solidify U.S. manufacturing leadership under initiatives like the CHIPS Act.”
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Tags: Advanced Packaging, Intel Foundry, Selective Layer Transfer, Subtractive Ruthenium, Transistor Scaling, Trillion-Transistor Era No Comments »
Monday, February 19th, 2024
David Abercrombie
By David Abercrombie
In motor car racing, many people think the win happens on the track, with lightning-fast pit stops ensuring the fastest car takes the black and white checkered flag at the finish line. In reality, the win happened long ago, in the garage, as the car was built and tested and rebuilt. The same is true in integrated circuit (IC) design. Getting a design through a successful tapeout on schedule isn’t just the result of signoff verification. It begins much earlier, back in the design and implementation stages. Finding and correcting critical errors in these early design stages helps design teams make adjustments quickly while layouts are still more open and flexible, avoiding time-consuming and complex fixes during signoff that can play havoc with delivery schedules.
But what happens when that early verification doesn’t match signoff verification? Despite all the work designers put in during the design stages, they may find themselves still trying to fix those hard errors, only now they’re constrained by layout restrictions, and under the gun to meet the schedule. Calibre® shift left (early design-stage) solutions bring industry-leading Calibre signoff-quality verification and design optimization into the design and implementation environments. Shift left verification and optimization can help design teams minimize those late-stage signoff iterations while still delivering high performance, high reliability designs. Using the same qualified rule decks and underlying engines used by the signoff toolsuite, Calibre shift left tools and technology deliver targeted verification that hones in on those errors most critical in early-stage designs, provide thorough analysis of complex design constraints, support designers with guided debugging to enable optimal fixes that remain signoff-compliant throughout the design flow, and apply selective automated design optimizations, all within a user-friendly toolset integrated into the designer’s design or implementation environment.
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Tags: Caliber, Siemens Comments Off on Winning doesn’t happen at the finish line, even in IC verification
Tuesday, October 31st, 2023
Apple has once again pushed the boundaries of innovation with the launch of its latest MacBook Pro lineup. Featuring the all-new M3 family of chips, including the M3, M3 Pro, and M3 Max, these laptops promise to deliver unprecedented performance and capabilities. From students to creatives, coders to machine learning programmers, Apple’s new MacBook Pro is set to revolutionize the way we work and play. In this article, we will dive deep into the details of this groundbreaking release, explore the capabilities of the M3 family of chips, and discuss how these laptops cater to a wide range of users.
MacBook Pro with M3 enables users to compile and test millions of lines of code in Xcode with even greater speed.
The M3 Family of Chips
Apple’s M3 family of chips represents a monumental leap in silicon technology. These chips are the first to utilize the industry-leading 3-nanometer technology, promising faster and more efficient performance. The GPU architecture in these chips is a game-changer, thanks to a groundbreaking technology called Dynamic Caching. This innovation allocates local memory in hardware in real time, optimizing memory usage for each task. The result is a dramatic increase in GPU utilization and performance, especially in resource-intensive applications and games.
Additionally, the M3 chips introduce new rendering features, such as hardware-accelerated mesh shading and ray tracing, which were previously unavailable on Mac. These features enhance the visual complexity and realism of scenes in games and other applications.
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Tags: Apple, M3 Comments Off on Unveiling Apple’s Game-Changing MacBook Pro with M3 Chips
Wednesday, January 4th, 2023
Donna Moore, CEO and Chairwoman, LoRa Alliance
By Donna Moore, CEO and Chairwoman, LoRa Alliance
2022 was truly a transformative year for IoT, yielding major shifts in perception and execution, and surpassing milestones of massive deployments. At the LoRa Alliance, our experience was that people moved away from asking about “what” LoRaWAN is, to asking about “how” to deploy, how to find devices, how to partner, how to achieve ROI. IoT clearly has moved into a new stage of mass adoption.
The execution and results of LoRaWAN proof of concepts (PoCs) provide evidence of this market shift. Previously, deploying a PoC took an average of 12 to 18 months. Now, it averages about 6 months. Even better, the ROI on LoRaWAN projects is usually higher than what was originally estimated. Organizations that complete these PoCs quickly realize that the fastest way to compound value is to add new use cases and optimize their operations to benefit from the efficiencies that the solution is providing.
The tremendous headwinds over the past few years—Covid-19, climate change, flooding, fires, droughts, labor shortages, inflation, supply chain constraints—became tailwinds for LoRaWAN technology. In response to the world’s struggle to maintain systems and processes that support daily life, LoRaWAN was deployed to alleviate the problems. LoRaWAN is now used to monitor air and food quality; water quality and availability; infrastructure; and safety, security and health, and much more. While supporting people and the planet, LoRaWAN drives efficiencies that promote business growth and financial stability, making it the leading IoT connectivity solution.
So, what does 2023 hold? The fact is that the world continues to face a growing list of challenges. A major focus in 2023 will be improving infrastructure – buildings, utilities and cities need to find solutions to enhance and improve existing systems that are too expensive to replace outright. When business and governments plan their solutions, they will choose LPWAN IoT and there is huge opportunity for LoRaWAN because of the considerable ROI it generates.
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Friday, October 28th, 2022
Interview with Christian Eder, Director Product Marketing at congatec and Chairman of the COM‑HPC Workgroup of PICMG
The PICMG presented the new COM-HPC Mini standard at the recent embedded world trade show. What features does this latest expansion of high-performance computing module standards offer?
Christian: The most significant innovation is that there is now a high-end form factor for credit-card-sized Computer-on-Modules. Like all other COM-HPC module standards, it is positioned above the performance classes targeted by COM Express. So, as far as credit-card-sized modules are concerned, it is positioned above COM Express Mini. The new COM-HPC connector supports transfer rates of more than 32 Gbit/s, which means that it fully covers PCIe Gen 4 and Gen 5, and probably even Gen 6. The interface selection includes a plan for 16 such PCIe lanes, in addition to three graphics interfaces and various fast USB 3.2 or USB 4.0 interfaces. That packs extremely high performance into such a small computing module.
The third generation of credit-card-sized modules is coming: Despite their small dimensions – 95 x 60 mm, according to the current plan – COM-HPC Client modules in Mini format will offer a comprehensive set of interfaces. On the roadmap are, among others, 16x PCIe, 3x graphics and several USB4 interfaces.
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Monday, May 16th, 2022
McKinsey, in a December 2021 AI survey, came up with a few conclusions that are worth paying attention to: 1) Nearly two- thirds of the respondents said that their companies’ investments in AI will continue to increase over the next three years 2) Over 64% also run their AI workloads on public or hybrid cloud.
DAC, for the very first time, is offering a unique hands-on workshop for Data Scientists. In this workshop offered by Catalit, Data Scientists (and aspiring Data Scientists) will learn how to formulate, train and improve ML models, by using both classic and deep learning algorithms.
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Monday, August 30th, 2021
This year we are experiencing many first with respect to planning the 58th Design Automation Conference. It’s the first DAC to be rescheduled from its normal summer schedule to December. It’s the first DAC to co-locate with both the RISC-V Summit and SEMICON West. And it is the first DAC to ever go hybrid with both a live and virtual component.
For this year’s Hybrid DAC, we incorporated many lessons learned from last year’s purely virtual DAC. The first lesson learned was that it is not possible to recreate the full experience of a live conference in a virtual world. Indeed, conferences such as DAC attract a global audience, and accommodating multiple time zones must be carefully factored into the plan. In addition, not every activity at a live conference translates into a good virtual experience. So, we learned the importance of providing a good digital journey through a conference by focusing on high-quality technical content.
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Saturday, August 7th, 2021
We did it! After over a year’s worth of hard work the DAC Executive Committee finally released the 58th DAC program! And in spite of a mountain of challenges and hurdles we encountered along the way this past year I couldn’t be prouder of the entire team involved in this major milestone.
We started planning the 58th DAC a little over a year ago, and we were confronted with a lot of uncertainty on what to expect for the coming year. Would submissions be down? Would we be able to find inspiring technical speakers to participate in a live event? But we did it!
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Friday, December 4th, 2020
The Designer and IP tracks have been a vital part of the DAC program since 2010, and I am honored to chair the Designer, IP and Embedded tracks for the 58th DAC. The Embedded track was added to the program last year to highlight this growing topic area in the design community.
Putting on DAC is a huge undertaking, and much of the work involved is done by volunteers from industry and academia. Each track contains submitted work as well as special invited sessions. The Designer, IP and Embedded tracks are co-chaired by Natarajan Viswanathan of Cadence Design, Monica Farkash of AMD, Randy Fish of Synopsys and Mark Kraeling of GE Transportation. Each track also has its own subcommittees to review and plan the year’s program. You can see who’s who on the DAC Executive Committee here.
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Monday, October 19th, 2020
Typically, people use the phrase “Rome wasn’t built in a day” to remind others that time is required to create something truly great. Now, what does this have to do with the Design Automation Conference? While it might seem like we held the 57th DAC just a few weeks ago, time doesn’t stand still. In fact, the 58th DAC team began laying bricks for next year’s event by holding its first kickoff meeting only three weeks after completing this year’s virtual event. And for the 58th DAC, I am truly honored to serve as General Chair. This is a big pair of shoes to fill when you consider the amazing 57 chairs who served before me.
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