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Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

Streamline 3D IC verification with a shift-left strategy

June 13th, 2024 by Sanjay Gangal

Unlike traditional integrated circuit (IC) designs, multi-dimensional 2.5D and 3D ICs are composed of multiple individual chiplets, each built to a separate process node best suited for its specific purpose. There are many different design options for connecting these chiplets, and any or all of these approaches can be combined on a single 3D IC assembly. This results in multiple components of different materials integrated in all three dimensions, which creates new and unique verification challenges for 2.5/3D IC designers.

3D IC assembly flow

Multi-dimensional ICs are one part of the industry’s answer to moving beyond the limits of Moore’s law. While 2.5D approaches, particularly chiplets placed upon a silicon interposer, have gained broad adoption, the move to true 3D IC is still early in its design lifecycle. Design tools and best design practices continue to evolve and improve, but many challenges are yet to be resolved.

In a true 3D IC, early design and package planning can be a challenging task, as the specific approach, materials, and chiplet placements used will induce thermal and mechanical stresses that can impact the intended electrical behavior of the full assembly design (Figure 1). Selecting the optimal approach and optimal chiplet placements becomes critical, implying multiple iterations will be required to determine the best final design.

Figure 1. Packaged 3D IC with non-uniform power distribution.

3D IC physical verification

Physical verification (PV) of 2.5/3D IC designs faces novel challenges. A typical 2.5/3D IC PV flow starts with dedicated verifications of each chiplet against their assigned foundry process requirements. In one sense, this is similar to verifying blocks independently before incorporation into a full system-on-chip (SoC) design. Where 3D IC PV diverges from a traditional SoC PV flow is in the full assembly verification. For layout vs. schematic (LVS) verification, a source netlist is needed. Historically, the assembly netlist takes the form of a comma-separated-value (CSV) or spreadsheet, where each pin is listed with its coordinates, a pin-specific name, and the name of the assembly-level net to which it is associated. This netlist is typically created manually, introducing a great deal of uncertainty with the possibility of human error.

When it comes to verification, the most common approach for checking physical and electrical compliance for a 3D IC requires the use of separate rule decks for design rule checking (DRC), LVS, etc., for each interface within the package (chip-to-chip, chip-to-interposer, chip-to-package, interposer-to-package, etc.). These rule decks typically use pseudo-devices, commonly in the form of 0 ohm resistors, to identify the connections across each interface while still preserving the individual chiplet-level net names.

However, the multiple deck approach creates its own set of challenges. Designers must associate the many individual rule decks to the corresponding interfaces within the assembly layout, which may not always be intuitive. As errors are identified, designers must be able to highlight them at the proper interfaces (with proper handling of rotations and magnifications) to help identify the appropriate fixes. With multiple dedicated rule decks and verification runs, keeping track of which results correspond to which interfaces and having confidence that the full assembly is correct is again time-consuming and wrought with the possibility of human error.

The use of pseudo-devices also presents additional challenges to designers, the first being how to introduce these pseudo-devices into the schematic or source netlist. This insertion is often manually performed, introducing yet more risk of human error. Pseudo-devices can also cause issues with the LVS checking at the interfaces to ensure correspondence to the layout. From a debug perspective, when there are connection issues, the separation created by such devices makes it difficult to properly trace the full connectivity across chiplets. In other words, the connected net between two chiplets is still seen as two separate nets, making probing (and ultimately debug) difficult. Finally, the presence of these pseudo devices, even 0 ohm resistors, can have unintended impacts when it comes to static timing analysis tools, as a single connection is again seen as two separate nets that must be passed into Verilog.

Finally, the use of these interface rule decks (particularly for LVS and subsequent electrical analyses) makes it practically impossible to generate a full assembly post-layout netlist or to otherwise understand electrical interactions across multiple components. For example, consider checking for adequate protection devices against electrostatic discharge (ESD) using an electronic design automation (EDA) tool like the Calibre® PERC™ reliability platform. Without a holistic assembly approach, it is impossible to verify ESD protection when the ESD circuits exist in one chip and the protection devices exist in another. Similarly, like a traditional SoC, assembly approaches to metallization from packaging or backside metal can create charge that may create antenna impacts. Given these metals may ultimately connect to multiple chiplets of heterogeneous processes, how can assembly designers possibly verify and protect against such yield and reliability issues using interface-only rule decks?

Shift left IC design and verification

To bring more advanced IC designs to market faster, and achieve the ramp to volume production sooner, Calibre Design Solutions provides tools and functionalities that enable design companies to implement “shift left” physical verification and design optimization earlier in their design and implementation flows (figure 2).

Figure 2. Calibre Shift Left design solutions help design teams enhance productivity and design quality while reducing time to market.

At Siemens EDA, we collaborate with design companies and foundries every day to understand what designers need and want to achieve business and design goals, and to provide an electronic design automation (EDA) ecosystem that supports every designer where they are with the tools they need. While many of the physical verification challenges facing 3D IC designers are unique to multi-dimensional designs, the same tools and functionalities can be applied to enable 3D IC design teams to perform accurate and efficient physical verification on these assemblies.

Using the trusted Calibre nmPlatform in conjunction with other tools from the Siemens EDA portfolio, 2.5/3D IC design teams have the freedom and flexibility to create a best-in-class shift left solution that improves designer productivity and design quality, provides faster runtimes and increased resource efficiency, and allows their designers to work within familiar design and implementation environments, all while achieving Calibre confidence throughout the design implementation flow.

Shift left for 3D IC physical verification

True 3D IC verification of physical and electrical constraints requires a holistic assembly-level approach. Enabling such an approach requires adherence to appropriate design stage requirements. 3D IC designers, like IC/SoC designers, have options that help them optimize their 3D IC designs and perform physical verification earlier in the 3D IC flow, enabling them to find and eliminate assembly issues when changes are easier to apply.

Figure 3. Some of the advanced package layouts designers can specify in Xpedition Substrate Integrator.

First, using a tool like the Xpedition Substrate Integrator (XSI) software, 3D IC designers can specify several different kinds of 3D floorplans (figure 3). While not all the detail for all the layers and materials will be available, it is still sufficient for early analysis to help rule out configurations that contain serious flaws. Using uniform materials, and simplified (or even uniform) power maps, designers can at least eliminate some design configurations from consideration.

A holistic approach requires full knowledge of both the 3D IC assembly and the individual chiplet processes. The most obvious challenge is how to ensure that the active chiplets in a 3D IC assembly will behave electrically as intended. Of course, LVS-level verification requires an assembly-level source netlist. Designers can create this netlist using automated approaches in the form of Verilog, or generate it from traditional package tools in other industry-standard formats. In Calibre verification, this issue is addressed by extending the already widely adopted infrastructure in place with the Calibre 3DSTACK tool to generate an assembly description that defines the 3D stackup using the Calibre 3DSTACK+ tcl text-based format. For complex assemblies, this description generation can be automated using such tools as the XSI design planning tool. Alternatively, newer formats such as the 3Dblox™ standard can also encapsulate such information.

With these options, a 3D IC physical verification approach becomes possible. This knowledge of the stack-up allows the Calibre engine to understand the connectivity and geometric interfaces across all components in the assembly, enabling a single deck and single run to not only identify and display DRC and LVS issues in a single results output, but also use the data captured during the individual chiplet-level LVS and similar runs, combined with the top assembly-level extraction data, to generate a post-assembly netlist for further analysis. This understanding of the assembly can also drive automation of cross-die parasitic coupling impacts and enable full assembly analyses, including not only ESD and antenna issues, but also extending to capture thermal and mechanical stress impacts on the 3D IC electrical behavior.

Mechanical stresses and temperature changes can affect electrical behavior. These impacts apply to active devices, changing device mobilities and conductivities, as well as to passive devices, impacting resistivities and electromigration (EM) impacts. In a traditional IC/SoC design, these impacts are largely safeguarded by the fact that all devices are within the same silicon die, and while there may be some small metal densities and other structural differences, most thermal changes occur across the full design. Similarly, mechanical stresses can vary, but not greatly.

In a 3D IC design, particularly in a true 3D stack, the thermal and mechanical stress impacts are very different. For example, a chiplet on the bottom of the stack might be solder-bonded to a package substrate, while the next chiplet is bonded face-to-back through bumps or copper pillars, and the next layer might be face-to-back or even face-to-face bonded using a direct hybrid bonding approach. With different materials, there will be different rates of thermal expansion and contraction, as well as mechanical stress impacts from different types of bonding material and adhesion interfaces.

While simple rules of thumb are often used to gain insight into such impacts, Calibre provides a comprehensive approach. Using the same assembly definition used in the Calibre 3DSTACK tool, the Calibre 3DThermal tool performs detailed thermal analysis, using the exact knowledge of all layers and materials, leveraging the detailed layer information of each individual chiplet. The thermal extraction performed by Calibre 3DThermal generates thermal models and thermal maps that can be fed to device-level thermal simulators. While the tools used to perform such simulations vary, the idea is the same: accurate layer and material information in the thermal extraction tools provides improved results. These thermal maps are then used to capture and understand thermal impacts of device behavior, driving more accurate performance, noise, and EM analysis, and, ultimately, enabling more accurate static timing analysis and faster chiplet-level signoff.

In a similar fashion, the Calibre toolsuite can also address mechanical stress impacts. Designers can add mechanical stress properties to the stackup definition, enabling Calibre to generate stress maps for the full assembly, which can be used by device-level mechanical stress analysis tools. These results can then drive extraction of mechanical stress impacts to the device level, which again feed into performance and reliability analyses.

Integrated cross-domain solutions

While 3D IC design and verification presents unique challenges, it also provides a prime opportunity for optimization and collaboration across multiple design and analysis domains. Thermal and mechanical stress impacts must be considered in conjunction, as they have direct impacts on each other and on the electrical behavior of the design. In a multi-dimensional design, it is critical to have a unified approach to understanding and analyzing these interactions to prevent late-stage design changes that can be costly and time-consuming.

With the Calibre 3DSTACK and Calibre 3DThermal tools, designers can perform early thermal and mechanical stress extraction and analysis, feeding these results into device-level simulators to understand their impacts on device performance. This cross-domain approach enables designers to identify potential issues earlier in the design process, allowing for adjustments and optimizations that are easier and less expensive to implement. The Calibre tools are also integrated with the industry-leading Simcenter Flotherm package/system thermal analysis solution, providing a full die-package-system level thermal analysis.

By automating these cross-simulation processes, the Calibre toolsuite allows for iterative and comprehensive analysis of thermal and mechanical impacts, providing accurate results that drive improved design decisions. This shift left approach ensures that 3D IC designs are robust and reliable, meeting performance and reliability requirements while minimizing the risk of late-stage issues and design iterations.


As the semiconductor industry continues to push the boundaries of design with multi-dimensional 2.5D and 3D ICs, the need for advanced verification tools and methodologies becomes increasingly critical. Siemens EDA’s Calibre solutions provide the necessary tools and capabilities to perform early and accurate analysis, debug and verification. The shift left in verification processes result in increased design flow efficiency and faster time-to-market. By leveraging the comprehensive Calibre toolsuite, 3D IC designers can overcome the unique challenges of multi-dimensional design, ensuring their products meet performance, reliability, and time-to-market goals.

For more information about how Calibre solutions can help you streamline your 3D IC design and verification process, visit our Shift left with Calibre solutions website. Explore our shift left resource library for access to papers, videos, and other resources that can help you optimize your verification processes.

Category: Chip Design

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