Posts Tagged ‘Synopsys’
Monday, February 17th, 2014
Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.
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Tags: 3D ICs, Cadence, Chip Design, EDA, EDA & IP, Electronic Design Automation, FinFETs, foundries, foundry, Intellectual property, Lee Public Relations, Mike Demler, Moore's Law, Semiconductor IP, semiconductors, SoC, Synopsys, System on Chip, The Linley Group, wearables, www.leepr.com
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Monday, April 15th, 2013
 McKenzie Mortensen |
 Darcy
Pierce |
 Hannah Watanabe |
For more than several years now, Peggy Aycinena has noted the dearth of new blood entering the EDA and IP industry ranks. Those of us who started in the industry in the 1980s still seem to dominate the corporate, engineering and marketing ranks. One area where we do see an infusion of new generation folks is in the marketing communications area. So Liz Massingill and I asked three of the new generation people to allow us to put them on the spot and talk a little about what new and old generation EDA and IP people bring to the party. With us are: McKenzie Mortensen of IPextreme, Darcy Pierce of Synopsys and Hannah Watanabe of Synopsys.
Ed: McKenzie, Darcy, Hannah, thanks for taking the time to speak with us today. So let’s kick off with a question about you. What does the new generation bring to EDA and IP that the old generation doesn’t?
McKenzie: We love to shake things up.
Darcy: One of the more obvious attributes that I think our generation brings to the table is a fresh perspective, especially in the “older” industry of EDA where everyone seems to have 20+ years of experience.
Hannah: I think we bring a fresh perspective on how technology is being used today, especially by those who are just entering the work force, the Generation Y people.
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Tags: EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?fref=ts, Intellectual property, IP, IPextreme, social media, Synopsys
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Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
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Tags: EDA, Electronic Design Automation, granularity, hardware, low power, low-power verification, Moore's Law, power, RTL, semiconductors, software, Synopsys, UPF, verification
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Monday, January 28th, 2013
The next entry in our prediction series comes from Karen Bartleson, esteemed blogger, standards proponent, social media guru and Sr. Director of Community Marketing at Synopsys:
 Karen Bartleson
2013 will be the year when people stop saying “engineers don’t use social media.” The data will show that indeed, they do use social media for both personal and work purposes. Not all engineers use it and some never will, but the way people live and work has changed. Engineers who are savvy about the modern ways that people communicate are seeing the benefits of incorporating social media into their regular activities.
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Tags: EDA, EDA social media, Electronic Design Automation, social media, Synopsys
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Wednesday, August 8th, 2012
 We’ve heard from Jim Hogan and Gary Smith on recent acquisitions. Now industry analyst Mike Demler weighs in.
Ed: What does the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Mike: It probably goes without saying that these two acquisitions are very different, both in their objectives and impact on the industry. The bottom line on the NextOp acquisition is that it represents strategic maneuvering by Atrenta as they attempt to emerge from their 10-year gestation period, which is generally the limit for VC-funded startups. I provide a more detailed analysis in an Analysis Brief, which is available from the EE Daily News.
The Synopsys-Springsoft acquisition may finally fill the hole in analog/custom implementation that Synopsys has had. When the Laker tools came on the landscape, they immediately gave Cadence some competition for Virtuoso. Synopsys has never been able to accomplish that with Galaxy Custom Designer, nor its predecessor (Cosmos).
Ed: What sort of new day does it herald for EDA?
Mike: As far as meaning to the EDA industry overall, again there are two different answers. For Atrenta-NextOp, this serves as a bellwether for the entire group of ~10-year old EDA startups. What are their exit strategies?
For Synopsys-Springsoft, the answer is more complex, and goes beyond the immediate impact in the analog/custom design space. With ~$1B in acquisitions in less than a year, Synopsys is looking more and more like a huge EDA conglomerate. They are separating themselves further from the 2nd and 3rd place companies, at least in terms of size. The industry dynamics will inevitably change as a result.
Ed: What’s the significance?
Mike: In a nutshell – the EDA industry continues to shrink. Acquisitions mean lost jobs. With 10-years or more now the norm to grow an EDA company, other industries look more attractive, both for capital investment and for skilled engineers.
Lee PR does work for Atrenta
Tags: Atrenta, EDA, EE Daily News, Electronic Design Automation, Finance, investments, Mike Demler. Semiconductors, RTL, Semiconductor IP, Springsoft, Synopsys
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Tuesday, August 7th, 2012
 Yesterday we heard from Jim Hogan on the NextOp acquisition. Today Gary Smith chimes in on NextOp and the recent Springsoft buyout.
Ed: What do the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Gary: Technology wise the Atrenta acquisition means that the Silicon Virtual Prototype is becoming a reality. Business wise it could be the start of the roll-up in the middle.
Springsoft was always a possible roller-upper but generally thought of as a long shot because of theirTaiwanheadquarters. Springsoft certainly makes Synopsys stronger, especially with the Laker analog product, but doesn’t affect the SVP or the RTL sign-off tool market. Debug is just being rolled up into the simulator.
Ed: What sort of new day does it herald for EDA?
Gary: With the creation of the SVP we now have the RTL sign-off established. This then is the breakpoint between design and implementation, just as the gate-level netlist was in the past. This will free up a large group of designers, and enable a new larger group of designers, which in-turn will cause the explosion of new systems development.
Ed: What’s the significance?
Gary: Growth, opportunity, money; the usual stuff.
Lee PR does work for Atrenta
Tags: acquisitions, Atrenta, buyouts, Chip Design, EDA, Electronics Design Automation, Finance, Gary Smith, NextOP, RTL, Semiconductor IP, semiconductors, Silicon Virtual Prototype, Springsoft, SVP, Synopsys
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Thursday, March 29th, 2012
This event is happening next week! Worth signing up if you can get down
there!………
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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Thursday, March 22nd, 2012
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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Thursday, February 9th, 2012
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com
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Monday, January 23rd, 2012
I believe that 2012 will be a challenging, but very interesting year. The pressure on the big EDA companies will definitely increase. Pressure coming from the shareholders, and from the users, who can play one against each other due to comparable offerings. From a technical point of view, the challenges keep rising at an even faster pace and less solutions are provided. I expect that the Synopsys/Magma merger will go through, which will take away an important piece of variety in the community. Consequently, this will increase the consideration of alternative solutions. This in return will help to improve or establish collaboration between EDA companies, leaders and smaller ones, and we might see teaming ups of some of the smaller ones to assemble packaged solutions to well-defined problems instead of proposing point tools. Despite this optimism, I expect that a lot of the smaller EDA tool providers will need to think out of the box in the future to survive.
Mathias Silvant
CEO
EdXact SA
www.edxact.com
Tags: 2012, EDA, EDA & IP, EdXact, Electronic Design Automation, Lee PR, Magma, Parasitics, semiconductors, Synopsys, www.leepr.com
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