Posts Tagged ‘software’
Wednesday, March 12th, 2014
Software is beginning to take on a bigger role in the SoC design world. How do we get to SW-HW co-verification? This topic was the center of discussion at a private event last week co-located with DVCon. The event, hosted by Jim Hogan and sponsored by Vayavya Labs Pvt. Ltd., included a panel discussion with Frank Schirrmeister (Cadence), Tomas Evensen (Xilinx) and Parag Naik (Saankhya). George Lotridge of VMware and Michael Bair of Intel also gave presentations. Click here for the presentations. (more…)
Tags: Cadence, Chip Design, device driver, EDA, Electronic Design Automation, Frank Schirrmeister, George Lotridge, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intel, Jim Hogan, Lee PR, Michael Bair, Parag Naik, Saankhya Labs, semiconductors, SoC, software, software-driven system-level verification, SW-HW co-verification, System on Chip, system-level verification, Tomas Evensen, Vayavya, VMware, www.leepr.com, Xilinx
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Wednesday, February 26th, 2014
 Retired senior vice president of Si2, Sumit DasGupta, imparts his sage view on what the semiconductor, EDA and IP industries should focus on to ensure a vibrant semiconductor industry for 2014.
“As the new year rolls out, there are promises and associated challenges that the semiconductor industry faces that need attention to ensure the vibrancy of the industry, even as the industry struggles to stay on the Moore’s law trajectory.
First in my list is the area of 2.5D and 3D integration, an area of great promise but with significant challenges. Much has been touted about these approaches as ways to deliver “More than Moore” but it appears to this observer to be advancing at a pace that is slower than hoped for. It seems to be just another year away from full production. But now, enough said, 2014 needs to be the year when much greater focus must be applied to get at least 2.5D technology into mass production. This is not a transitory approach to 3D but rather should last longer in its own right as a very viable technology sitting alongside 3D as 2 approaches to semiconductor integration. 3D still has challenges to be addressed but here again, greater focus needs to be applied to ramp up to full production in 2015.
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Tags: 2.5D, 3D, 3D IC, 3D ICs, 3D stacked die, Chip Design, EDA, Electronic Design Automation, Internet of Things, IoT, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, Si2, SoC, software, stacked die, Sumit DasGupta, System on Chip, www.leepr.com
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Tuesday, August 13th, 2013
Do you want to know the latest on ESL? Curious what today’s tools look like?
Gary Smith will be conducting a webinar this coming Monday on this very topic – ESL – are you Ready?
Gary, along with Mike Gianfagna of Atrenta and Jason Andrews and Frank Schirrmeister of Cadence, will examine the evolution of ESL over the past few years and share the breakthroughs that have occurred in the flow.
When is it?
11:00-11:45 am PDT
Monday, August 19, 2013
Gary will be recognizing the industry’s “ESL Heroes.” Want to know what an ESL Hero is? Tune in Monday to find out.
You can register for the webinar here.
Tags: Atrenta, Cadence, Chip Design, EDA, Electronic Design Automation, Embedded, ESL, Gary Smith, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Lee Public Relations, semiconductors, software
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Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
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Tags: EDA, Electronic Design Automation, granularity, hardware, low power, low-power verification, Moore's Law, power, RTL, semiconductors, software, Synopsys, UPF, verification
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Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”
See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:
EDA Café Blog: What Would Joe Do?
EDA Express
EE Daily News
EE Times News & Analysis
EE Times: EDA DesignLine
Gabe on EDA
SemiWiki
System-Level Design
Tech Design Forums
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Lee PR does work for Atrenta
Tags: Assertion Synthesis, Atrenta, EDA, EDA Cafe, EDA DesignLine, EDA Tech Design Forums, EE Daily News, EE Times, Electronic Design Automation, Gabe on EDA, Gary Smith, Jim Hogan, M&A, NextOP, NextOp Software, register transfer level, RTL, Semiconductor IP, semiconductors, SemiWiki, software, System-Level Design, verification
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Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
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Thursday, February 9th, 2012
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com
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Wednesday, January 25th, 2012
On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power — I think we’ll see a move to optimize for power as a primary consideration.
On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.
On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics — a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes 🙂
Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com
Tags: 2012, ASIC, EDA, EDA & IP, EE Times, Electronic Design Automation, FPGA, Lee PR, low power, Maxfield High-Tech Consulting, Programmable Logic, Programmable Logic DesignLine, publishing, semiconductors, SoC, software, SRAM, System on Chip, textbooks, www.leepr.com
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