Software is beginning to take on a bigger role in the SoC design world. How do we get to SW-HW co-verification? This topic was the center of discussion at a private event last week co-located with DVCon. The event, hosted by Jim Hogan and sponsored by Vayavya Labs Pvt. Ltd., included a panel discussion with Frank Schirrmeister (Cadence), Tomas Evensen (Xilinx) and Parag Naik (Saankhya). George Lotridge of VMware and Michael Bair of Intel also gave presentations. Click here for the presentations. (more…)
Posts Tagged ‘Saankhya Labs’
“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense. Here is why.
‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs. Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.
The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. (more…)