Next up in our series is Simon Bloch’s forecast for 2014. Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.
“The future of electronics is looking bright! Market forecasters predict growth in literally every category of electronic markets ranging from smart mobile and wearable devices, appliances and sensors connected to a network of Internet of Everything to smart connected cars and cities.
In today’s electronics products, sophisticated hardware is becoming insufficient for product success. Many layers of stacked software control the underlying hardware and determine a product’s competitiveness via functionality, performance, power and cost. And while there is always going to be a need to create new semiconductor components and IC companies will need EDA tools, EDA vendors need to expand the view of Electronics and treat software stack as an integrated part of EDA.
There are many opportunities to come up with products in the software stack space around Linux/Android operating systems and in the area of hardware virtualization. Just last month, CyanogenMod, a company that provides Android based software widely used in the mobile industry, secured $23 million in funding from top tier VCs. CyanogenMod is a software stack product and contains many features not found in Google versions of the operating system.
We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….
“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models. Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.
My colleague Liz Massingill spoke with IPextreme CEO Warren Savage about her approach to PR, i.e., what she wants to accomplish on behalf of her clients.
The main message? It’s all about the story…the company’s story…and how Liz creates it, substantiates it, reinforces it. In the end, it’s all about putting a human face on the faceless company to give it personality, an image, a life. An entity that customers want to do business with.
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
In the following video, Warren Savage, CEO of IPextreme, talks with Mike Gianfagna, VP of Corporate Marketing at Atrenta, about collaboration – with TSMC and the Constellations partners.
Mike’s dream is for “a vibrant industry with a well-defined quality metric.”
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren Savage President and CEO IPextreme
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……
For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.
These two trend setters share their opinions on the BIG DACthemes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
Next up in our series is Simon Bloch’s forecast for 2014. Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.
