Archive for the ‘Uncategorized’ Category
Tuesday, May 6th, 2014
You’ve got problems with your design rule deck? See what Bryon Moyer and Peggy Aycinena have to say on how to fix those problems……
Testing Out the Rules by Bryon Moyer
Sage-DA: Automating rule checking by Peggy Aycinena
Come check out Sage-DA at Booth 1423 at the Design Automation Conference.
Lee PR does work for Sage-DA.
Tags: automatic rule checking, Chip Design, DAC, Design Automation Conference, DRC, DRC decks, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Sage Design Automation, Sage-DA, semiconductors, SoC, System on Chip, www.leepr.com
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Wednesday, April 30th, 2014
In a recent blog entry we asked Chris Rowen, Cadence Fellow and Tensilica Founder, to share with us what EDA and IP (as an industry) need to do in 2014 to serve its user base better. The following is a follow-up blog by Rowen explaining how.
System-design Evolution Follows the Data
When last we chatted in this forum, I responded to a question Ed Lee proposed to this as part of the Predictions 2014 series: What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?
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Tags: Cadence, Chip Design, Chris Rowen, EDA, EDA & IP, EDA tools, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, IP blocks, IP vendors, microprocessor design, semiconductor design, Semiconductor IP, SoC, System on Chip, Tensilica, www.leepr.com
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Monday, March 17th, 2014
 RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern. I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.
Liz: Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.
Piyush: No problem, Liz
Liz: So, to start out, what is RTL Signoff?
Piyush: “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge. Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.
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Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Piyush Sancheti, register transfer level, RTL, RTL signoff, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com
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Sunday, March 16th, 2014
 Brian Fuller - editor in chief of the now-lamented EE Times during its best years - and I were talking about it being great that there are these predictions about where EDA/IP is going in 2014. Chris Rowen’s wrap up prediction talked about EDA’s need to move beyond component – level focus. Chris isn’t alone in this idea.
The question is: HOW will EDA/IP get beyond the component level and start looking at what’s beyond the 25-year EDA horizon and how EDA can and must add value.
Brian and I would love to hear what readers out there think…..
Does EDA & IP need to go beyond?
Where does it need to go?
And how will it get there?
Tags: Brian Fuller, Cadence, Chip Design, Chris Rowen, EDA, EDA & IP, EE Times, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com
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Wednesday, March 12th, 2014
Software is beginning to take on a bigger role in the SoC design world. How do we get to SW-HW co-verification? This topic was the center of discussion at a private event last week co-located with DVCon. The event, hosted by Jim Hogan and sponsored by Vayavya Labs Pvt. Ltd., included a panel discussion with Frank Schirrmeister (Cadence), Tomas Evensen (Xilinx) and Parag Naik (Saankhya). George Lotridge of VMware and Michael Bair of Intel also gave presentations. Click here for the presentations. (more…)
Tags: Cadence, Chip Design, device driver, EDA, Electronic Design Automation, Frank Schirrmeister, George Lotridge, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intel, Jim Hogan, Lee PR, Michael Bair, Parag Naik, Saankhya Labs, semiconductors, SoC, software, software-driven system-level verification, SW-HW co-verification, System on Chip, system-level verification, Tomas Evensen, Vayavya, VMware, www.leepr.com, Xilinx
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Monday, March 3rd, 2014
 For our final entry to this series, let me just reiterate our original question…..
What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?
Chris Rowen, Cadence Fellow and Tensilica Founder, will wrap it up with his word on the subject.
“What does the EDA and IP industry need to do in 2014? Simply put, we need to move past EDA.
Let me explain. As an industry, we’re not just about ‘how’ you design something; we’re increasingly about ‘what’ you design.
This comes amid the relentless march of design complexity. It also comes as companies reconsider their position in the electronics ecosystem to try to deliver more value for customers.
For instance, semiconductor vendors are considering where they best fit into the design spectrum and they’re also looking farther upstream to understand market requirements of their customers’ customers. IP providers, for their part, are looking upstream to understand marketing technology requirements better and re-engineering their business models.
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Tags: Cadence, Chip Design, Chris Rowen, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, IP, Lee PR, Semiconductor IP, semiconductors, SoC, System on Chip, Tensilica, www.leepr.com
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Wednesday, February 26th, 2014
 Retired senior vice president of Si2, Sumit DasGupta, imparts his sage view on what the semiconductor, EDA and IP industries should focus on to ensure a vibrant semiconductor industry for 2014.
“As the new year rolls out, there are promises and associated challenges that the semiconductor industry faces that need attention to ensure the vibrancy of the industry, even as the industry struggles to stay on the Moore’s law trajectory.
First in my list is the area of 2.5D and 3D integration, an area of great promise but with significant challenges. Much has been touted about these approaches as ways to deliver “More than Moore” but it appears to this observer to be advancing at a pace that is slower than hoped for. It seems to be just another year away from full production. But now, enough said, 2014 needs to be the year when much greater focus must be applied to get at least 2.5D technology into mass production. This is not a transitory approach to 3D but rather should last longer in its own right as a very viable technology sitting alongside 3D as 2 approaches to semiconductor integration. 3D still has challenges to be addressed but here again, greater focus needs to be applied to ramp up to full production in 2015.
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Tags: 2.5D, 3D, 3D IC, 3D ICs, 3D stacked die, Chip Design, EDA, Electronic Design Automation, Internet of Things, IoT, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, Si2, SoC, software, stacked die, Sumit DasGupta, System on Chip, www.leepr.com
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Monday, February 24th, 2014
Next up in our series of predictions Warren Savage, President and CEO of IPextreme, shares with us what he sees in his crystal ball for 2014.
“As the door closes on a successful 2013 for most companies in the semiconductor industry, the outlook for 2014 is bright as we see an explosion of new devices in the so-called “Internet of Things” era. Google’s recent $3.2B acquisition of Nest is indicative that this market will soon eclipse the smart phone/tablet era (aka the post-PC era). The IoT era will bring with it a range of new opportunities for semiconductor companies to exploit that are not mega-devices, but small, specialized technologies that enable opportunities in adjacent markets, like software and data analysis. There may be at least one semiconductor company that exploits this secondary and/or tertiary source of revenue. (more…)
Tags: Chip Design, Intellectual property, Internet of Things, IoT, IP, IPextreme, Semiconductor IP, semiconductors, SoC, System on Chip, Warren Savage, www.leepr.com
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Wednesday, February 19th, 2014
 Bob Smith, Senior VP Marketing & Business Development at Uniquify, shared with us his predictions for semiconductor IP in 2014.
“If 2014 has a watchword for the Semiconductor Industry, it would be momentum and that would be a result of the rapidly increasing use of IP in SoC designs. Add on the mushrooming need for ‘adaptive’ IP to mitigate timing and variation challenges in complex SoCs as performance issues multiply and process geometries shrink.
Moves within the DDR memory space continue to rock the industry and create momentum. Designers are heading directly to the latest JEDEC standard LPDDR4 (low-power DDR4) and moving beyond (or even skipping) LPDDR3 because they’re getting greater gains in performance and low power, an important consideration for mobile applications.
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Tags: Bob Smith, Chip Design, DDR, EDA, Electronic Design Automation, Intellectual property, IP, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, SoC, System on Chip, Uniquify, www.leepr.com
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Monday, February 17th, 2014
Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.
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Tags: 3D ICs, Cadence, Chip Design, EDA, EDA & IP, Electronic Design Automation, FinFETs, foundries, foundry, Intellectual property, Lee Public Relations, Mike Demler, Moore's Law, Semiconductor IP, semiconductors, SoC, Synopsys, System on Chip, The Linley Group, wearables, www.leepr.com
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