Posts Tagged ‘system verilog’
Thursday, June 15th, 2017
‘The cloud’ has been an industry buzz word for some time now and whilst the initial focus was on data storage and sharing – and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, Amazon Web Services (AWS), gives users access to servers and a range of applications. Storage is available as before but so too now are dedicated relational databases; which in Amazon’s case is provides through a different service.
Enterprise businesses are taking advantage of cloud computing platforms, and for a number reasons. These include pay-as-go (as opposed to investing considerable cap ex), speed and flexibility (resources and storage can be made available quickly), and one is spared the headache of maintaining a mass of IT hardware and keeping on top of software license renewals.
Also, earlier this year Amazon announced EC2 (Elastic Compute Cloud) F1, a compute instance with FPGAs that users can program to perform hardware accelerations. The F1 instance includes an FPGA developer Amazon Machine Image (AMI) which includes a development environment with scripts and tools for code compilation and design simulation.
It is expected the primary users of EC2 F1 will be software developers, working on complex and compute-intensive algorithms for which FPGAs lend themselves particularly well. For instance, High Performance Computing will increasingly exploit FPGA technology.
But let’s not forget one of the most important roles that FPGAs have been playing in our industry – EDA – for a number of decades: hardware acceleration for ASIC prototyping purposes.
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Tags: Active-HDL, Emulation, FPGA-based hardware emulation platform, hardware, Hardware Emulation, HES-DVM, mixed language simulations, SoC and ASIC Prototyping, system c, system verilog, utilise Virtex-7, verilog, VHDL, Virtex UltraScale FPGAs, Virtex-7
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Friday, March 18th, 2016
 The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?
You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with DUT in SystemVerilog using a DPI transactor, as defined by the Function-based.
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Tags: direct programming interface, IP, sce-mi, system c, system verilog, systemverilog
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Monday, August 12th, 2013
Fast Track to SystemVerilog for Verilog Users
The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.
Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!
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Tags: Aldec, design, design subset of systemverilog, fast track online trainings, simulation, system verilog, training, verification, verilog, VHDL
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Monday, June 24th, 2013
 Productivity Boosting Features
Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and to help them use it more efficiently.
There are two main categories for HDL editors (1) general purpose text editors, and (2) integrated text editors. Both have their own pros and cons, and in the end it is for each engineer to decide which suits their needs.
The HDL editor built into Active-HDL falls under the second category of integrated text editors. It offers many basic features (syntax highlighting, templates, columns selection, code folding, auto-formatting) as well as semantic features (code navigation, on-the-fly error detector), and also offers seamless integration with the simulator and version control system. The HDL editor in Active-HDL can be used with VHDL, Verilog, SystemVerilog, SystemC, C/C++, PSL, OVA, Perl scripts and Tcl scripts.
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Tags: Active-HDL, auto-formatting, c/c++, code analysis, code browser, code folding, code navigation, code template, columns selection, creating hdl text modules, HDL, hdl editors, on-the-fly error detector, ova, perl scripts, psl, syntax highlighting, system verilog, systemc, Tcl scripts, templates, value probes, verilog, VHDL
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Tuesday, June 11th, 2013
Functional Verification Insights from Austin
I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.
Conference itself
One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.
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Tags: cdc, dac, design automation conference, driver software verification, ecosystem partners, fpga-based prototyping, Functional Verification, high level synthesis, hls, hw/sw co-verification, mixed-signal simulation, multimillion gate soc, multiple clock domains, Riviera-PRO, SoC, SoC and ASIC Prototyping, SoC Verification, spec-tracer, system development, system verilog, systemverilog-based uvm, uvm-compliant environments, verification, verification ips, vips
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