Archive for the ‘SoC Design and Validation’ Category
Tuesday, May 10th, 2016
 Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.
Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.
A Basic ASIC Verification Flow
Managing verification for ASICs requires a well-defined verification plan. Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.
While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
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Tags: acceleration, asic, Emulation, linting, prototyping, simulation, SoC and ASIC Prototyping, verification
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Monday, April 20th, 2015
How to use VIPs In Practice
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.
Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.
Figure 1. Typical verification process
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Tags: Aldec, Emulation, HES-7, HES-DVM, ICE, In-circuit emulation, Kamil Rymarz, Monitor, Riviera-PRO, SoC Verification, Speed Adapter, Test, Transactor, Validation, Verification IP
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Tuesday, February 24th, 2015
This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning math, science, and technical skills.
I work with Generation STEAM, a group organized by the SYN Shop MakerSpace and the Henderson district library to create a series of STEM (Science, Technology, Engineering, [Art], and Math) classes that are free to the public. For my part, I’ve had the privilege of teaching a basic electronics class for kids a few Saturdays this year – and it’s been a blast. Our hope is that we are encouraging a few young people to follow the path of engineering.
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Tags: Aldec, Electronics Engineering, engineers week, future engineers, SoC and ASIC Prototyping, STEM
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Thursday, December 11th, 2014
Well folks, last call from Engineer Santa. Aldec’s #12DaysofUsefulGifts giveaway will end this Friday, December 12 at 12pm midnight Pacific Standard Time.[preview_cut]
If you haven’t registered yet, you’ll want to hurry and visit www.aldec.com/survey. There you will take a brief verification survey and be entered to win.
If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. If you are looking for some practical and useful gift ideas for the holidays, you might want to take a closer look. I’ve already talked about some of these from Days #1-4. We’ve given away more prizes since then and sent them to engineers all over the globe! Here, take a look…
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Tags: 1 Voice Beanie with Built-in Bluetooth Headphones, Aldec #12DaysofUsefulGifts giveaway, Anker Dual-Port Solar Charger, Anker Ultra Compact External Battery Charger, Etekcity Digital Laser Infrared Thermometer, Nike Air Jordan Hood Backpack Bag, SoC and ASIC Prototyping, XBOOM Ceramic Mini Portable Capsule Speaker
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Thursday, December 4th, 2014
Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!
If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.
To enter Aldec’s #12DaysOfUsefulGifts drawing, visit www.aldec.com/survey. There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!
Tags: air vent mount for cell phones, Aldec #12DaysofUsefulGifts giveaway, aldec winning prizes, bushnell falcon 7x35 binoculars with case, grillight led bbq spatula, magisso tea cup, miles kimball manual hand held shredder, pocketmonkey wallet multi-tool, professional cleaning set for dslr cameras, SoC and ASIC Prototyping, sugru hardware sealer
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Monday, October 20th, 2014
 Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.
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Tags: Aldec, automated and scriptable hybridverification, bit-level simulation acceleration, debugging, embedded, fabless semiconductor company, fpga ASIC prototypes, fpga-based emulation system, hardware emulation solutions, hardware prototyping, hes product, hes technology, hes usecases, HES-7, HES-DVM, SCE-MI 2.1 transaction emulation, sce-mi emulation, SoC and ASIC designs, SoC and ASIC Prototyping, uvm, validation environment, verification, virtual modeling
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Tuesday, June 24th, 2014
 If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.
Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.
Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, aldec 30th anniverssary, aldec 30th birthday party, dac 2014, dac chat, embedded, gopro hero3+ camera, Hardware Emulation, safety-critical, SoC and ASIC Prototyping, training, uvm, uvm methodologies, verification, vhdl verification using osvvm
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Friday, January 10th, 2014
 When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
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Tags: Active-HDL, aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
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Wednesday, December 11th, 2013
 Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.
 Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews. The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.
Our Commitment to the VHDL Community
When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Active-HDL, advanced verification platform, Aldec, aldec design rule checker, aldec dna, aldec simulators, alint, bitvis, do-254/ed-80 vhdl rule plug-ins, eda industry, embedded psl, FPGA Design, functional coverage, HDL, highest productivity to value ratio, ieee, ieee 1076-1993 Standard, ieee 1076-2002 vhdl standard, ieee 1076-2008 standard, ieee standard, ieee vhdl, intelligent testbench methodology, open source vhdl verification methodology, osvvm, psl embedded in vhdl, randomization, Riviera-PRO, simulation, source encryption, standards, starc vhdl, vector implementation of integer arithmetic, verification, VHDL, vhdl community, vhdl designs, vhdl testbench, vhpi interfacing to C/C++ code
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Wednesday, October 9th, 2013
In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure which is based on SystemVerilog DPI functionality. The SystemVerilog DPI is an interface which can be used to connect SystemVerilog files with foreign languages (C, C++, SystemC, etc).
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Tags: accelera, Aldec, Emulation, function-based infrastructure, HES-DVM, macro-based sce-miI, sce-mi macro-based infrastructures, SoC, soc design verification time, systemc, systemverilog, systemverilog dpi functionality, verification
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Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.
