Posts Tagged ‘RTL’
Tuesday, May 20th, 2014
As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.
It’s a Jim Hogan-moderated discussion event on
IoT system design concerns
Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3) sum up what we’ve learned during this session. Of course, this group of speakers are pretty opinionated and won’t need much provocation.
Monday, March 17th, 2014
RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern. I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.
Liz: Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.
Piyush: No problem, Liz
Liz: So, to start out, what is RTL Signoff?
Piyush: “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge. Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.
Monday, February 3rd, 2014
Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
Wednesday, August 28th, 2013
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
Click here for more information.
LPR does work for Atrenta
Tuesday, August 20th, 2013
We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.
However, making an error when specifying timing exceptions can possibly shut down a design project.
Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:
(Note: white paper download requires registration)
LeePR does work for Atrenta.
Monday, August 12th, 2013
Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.
It’s a tad more like Terminator 2 than the masked man and Tonto. And it may not be too far from reality – that’s what’s exciting…..and scary.
Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.
Click here to look into the future.
Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
Wednesday, October 10th, 2012
Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline. Along with number one article Understanding Clock Domain Issues by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.
So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges. Here’s what he had to say.
Ed: Narayana, your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say. What can you add to your July 2012 article?
Narayana: Thanks Ed. From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.
Ed: How so?
Narayana: UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.
Ed: So how best to deal with power intent?
Narayana: RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.
NOTE: For an update on Understanding Clock Domain Issues see our blog of October 3.
Note: Lee PR does work for Atrenta
Tuesday, September 4th, 2012
Atrenta CEO Ajoy Bose and EDA visionary and investor Jim Hogan spoke at a recent National Institute of Technology (NIT) meeting on the momentous changes we see in who controls chip design these days. Clearly, systems companies like Apple define – even dictate – what they want from their silicon vendors..and these systems customers certainly want a lot more than they did ten years ago.
Jim tells us why we have to care:
Video Part 1
Video Part 2
Power Point Presentation
Ajoy shows us how to care:
Video Part 1
Video Part 2
Power Point Presentation
Lee PR does work for Atrenta
Monday, August 20th, 2012
Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama. This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:
Lee PR does work for Atrenta