Posts Tagged ‘Cadence’
Monday, July 28th, 2014
In our continuing series on the IoT, Frank Schirrmeister of Cadence explains what three components of the IoT are important to him.
Schirrmeister: There are three components of importance. Fitbit. ARM’s going very big in that area, with their silicon partners. That’s not the IoT in its completeness. That’s an important component, but the analog mixed-signal components are certainly fun and challenging in this domain.
Then there are two more pieces to the Internet of Things that make me very happy, from a system design perspective: The first one is the hub of my data from the Fitbit. I have at least four hubs that I’m concerned about. My cell phone when I’m mobile. My computer at home. My living room; apparently my TV knows about my habits.
And there is my car. So that’s a hub – a very important piece. And from a system design perspective, there’s system development, emulation, FPGA, virtualization. There is a huge interesting market for us.
Then the third piece is this whole cloud space. That’s where the Intel, ARM, PC battle is waging. And that’s also a very important component of the Internet of Things where all the data crunching has happened and the health data that the health monitor needs to pick up. It is a very attractive market for EDA and will be very important to drive requirements, as well, for us.
Monday, July 21st, 2014
As we had previously announced, venture capitalist Jim Hogan moderated a panel at DAC regarding the IoT.
It was an eye opener about all things IoT……or maybe we should call it the IoE (The Internet of Everything), or as one prominent editor noted, the IoW (The Internet of Whatever). Our panelists included: Gary Smith, Market Analyst, GSEDA; Frank Schirrmeister, Group Director, System Development Suite, Cadence; Bernard Murphy, CTO, Atrenta; and Randy Smith, VP of Marketing, Sonics.
Very lively discussion among panelists, but also from the floor! Most notably editor Gabe Moretti of Chip Design and Simon Bloch of Samsung. Bloch, Sr. Director of R&D in mobile consumer wireless devices, posed questions and stimulated discussion to the point where he might be called the unannounced 6th panelist.
Over the next few blogposts, we’ll share snippets of that discussion. Gary Smith will start us off…..
Tuesday, May 20th, 2014
As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.
It’s a Jim Hogan-moderated discussion event on
IoT system design concerns
Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3) sum up what we’ve learned during this session. Of course, this group of speakers are pretty opinionated and won’t need much provocation.
Wednesday, April 30th, 2014
In a recent blog entry we asked Chris Rowen, Cadence Fellow and Tensilica Founder, to share with us what EDA and IP (as an industry) need to do in 2014 to serve its user base better. The following is a follow-up blog by Rowen explaining how.
System-design Evolution Follows the Data
When last we chatted in this forum, I responded to a question Ed Lee proposed to this as part of the Predictions 2014 series: What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?
Sunday, March 16th, 2014
Brian Fuller - editor in chief of the now-lamented EE Times during its best years - and I were talking about it being great that there are these predictions about where EDA/IP is going in 2014. Chris Rowen’s wrap up prediction talked about EDA’s need to move beyond component – level focus. Chris isn’t alone in this idea.
The question is: HOW will EDA/IP get beyond the component level and start looking at what’s beyond the 25-year EDA horizon and how EDA can and must add value.
Brian and I would love to hear what readers out there think…..
Does EDA & IP need to go beyond?
Where does it need to go?
And how will it get there?
Wednesday, March 12th, 2014
Software is beginning to take on a bigger role in the SoC design world. How do we get to SW-HW co-verification? This topic was the center of discussion at a private event last week co-located with DVCon. The event, hosted by Jim Hogan and sponsored by Vayavya Labs Pvt. Ltd., included a panel discussion with Frank Schirrmeister (Cadence), Tomas Evensen (Xilinx) and Parag Naik (Saankhya). George Lotridge of VMware and Michael Bair of Intel also gave presentations. Click here for the presentations. (more…)
Monday, March 3rd, 2014
For our final entry to this series, let me just reiterate our original question…..
What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?
Chris Rowen, Cadence Fellow and Tensilica Founder, will wrap it up with his word on the subject.
“What does the EDA and IP industry need to do in 2014? Simply put, we need to move past EDA.
Let me explain. As an industry, we’re not just about ‘how’ you design something; we’re increasingly about ‘what’ you design.
This comes amid the relentless march of design complexity. It also comes as companies reconsider their position in the electronics ecosystem to try to deliver more value for customers.
For instance, semiconductor vendors are considering where they best fit into the design spectrum and they’re also looking farther upstream to understand market requirements of their customers’ customers. IP providers, for their part, are looking upstream to understand marketing technology requirements better and re-engineering their business models.
Monday, February 17th, 2014
Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.