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 Aldec Design and Verification

Posts Tagged ‘debugging’

UVM. It’s Organized and Systematic.

Wednesday, February 10th, 2016

The-fundamentals-of-UVMOne of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamentals home.


UVM has a great structure and organization paradigm. I consider there to be two distinct and fundamental elements in the UVM structure: Components and Objects. Now this characterization isn’t strictly correct because uvm_components are extended from uvm_objects, but I think they are used in such a way that warrants the distinction. I consider it similar to the idea of trucks and cars. In my view, trucks are also cars, but it’s useful to note the difference.


How HES™ Technology Solved Problems for These Users

Monday, October 20th, 2014

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.


Much has changed in the last 30 years

Friday, January 10th, 2014

When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.

Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.

As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.


Effective Communication is Key in Relationships… and ESL Design!

Monday, November 25th, 2013

COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.

To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):

For the rest of this article, visit the Aldec Design and Verification Blog.


90’s Kid Active-HDL Celebrates Sweet 16

Wednesday, August 28th, 2013

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.

The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.


Working Smarter not Harder

Monday, July 22nd, 2013

To Accelerate DSP Design Development

If we’re being honest, human beings, especially engineers, are lazy. Let’s face it, most inventions ever made were created for the sole purpose of making our lives easier. The same goes for the manner in which we create our designs. In the not so distant past, engineers were drawing designs by hand on huge trace paper, placing them one below the other to form layers. This sounds like hard work to me! The lazy me would have wanted a smart (read: easy) solution to this process. Then along comes the EDA industry, which Aldec has been part of since 1984, making it much easier for us to do our designs.

Some might argue that EDA was born out not out of laziness, but in fact neccessity, due to increasing design complexity. True, it is impossible to imagine how the pencil and paper method could even work today. The point is it didn’t, and we now have automated the process to such an extent all you need do is enter some parameters in a tool wizard.


‘Wireless Algorithm Validation’ with Aldec and Agilent

Thursday, May 30th, 2013

Free DAC INSIGHT Presentation

Free DAC INSIGHT PresentationAt the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.


Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.


S2C: FPGA Base prototyping- Download white paper

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