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 Aldec Design and Verification
Sunil Sahoo
Sunil Sahoo
Sunil is Corporate Applications Engineer at Aldec. Sunil provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide … More »

Do I really need a commercial simulator?

 
March 26th, 2018 by Sunil Sahoo

As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t have funds to buy additional tools. I understand their situation and point out to them that at Aldec we have a very cost-effective simulator. But that is not what I want to talk about in this blog. I want to talk about engineers who say: “I am happy with the simulator my FPGA vendor provided me”, or “My simulations only take 15-20 minutes to run, I don’t think I need a faster simulator”, or “We don’t run simulations”.

That last response haunts me the most. For instance, at a recent site visit I was told: “We just load the design on our FPGA and test it out”. I asked how long does a full test iteration (i.e. program FPGA -> test -> debug -> re-code -> re-program) takes. They said about an hour or two, depending on the bug. I then asked how much of that time spent just running synthesis and programming the board? They said about 30 minutes.

Next, I proceeded to explain the benefits of running simulations in such scenario.

Granted, the test on the board will run much faster than a simulation, but you are very much limited by the peripherals that are hooked up to the board. For example, how quickly can you run a new test after one has just completed? Also, there is the matter of synthesizing and implementing the design every time you want to run a new test after a code change.

Imagine how much quicker you can run simulations because you don’t have to go through the above steps. If one tests fails, you could be running another in the background while you debug the one that failed. And let’s not forget the debug capabilities that simulations provide. These include the ability to access internal registers in the design, compare waveforms, and much more.

For the rest of this article, visit the Aldec Design and Verification Blog.

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Categories: Active-HDL, FPGA Design, FPGA Simulation, Functional Verification, Riviera-PRO

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