Aldec Design and Verification
Vatsal provides technical support for Aldec’s software products such as Active-HDL and Riviera-PRO. He is proficient in FPGA/ASIC digital design and verification.As a technical support engineer, Vatsal has deep understanding of verification languages such VHDL, Verilog/SystemVerilog, SystemC and … More »
Understanding the inner workings of UVM – Part 2
January 29th, 2018 by Vatsal Choksi
In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. If you need refresh your memory on where the classes Sequence, Sequencer and Drivers stand please click https://www.aldec.com/en/company/blog/149–understanding-the-inner-workings-of-uvm.
So, let’s look at the main concepts and follow the communication mechanism they use for the effective execution of a test.
What is Sequence? It is used to generate a number of Sequence_items; randomize the data fields used in Sequence_items and send it to the Sequencer on request. In order to maintain synchronization with the test-vectors, you can create more than one Sequence, each sequence having been assigned to a particular data-field or task. Sequence consists of REQ and RSP handles to the sequence_item. Basically, REQ is used to send a request to the Sequencer to send sequence_item to the driver. RSP is used as a response from the driver when it completes a particular operation. After writing a Sequence, it can be executed by calling start() in the test.
Fig 1 : N number of Sequences
Fig 2 : Top Level Structure of Sequence and Sequencer
Now there is an important property of Sequence to just touch on again, namely body().
When you call the start() function, some pre-defined callbacks get executed in order. Body() contains the majority of the part of those callback methods and hence it is an important property.
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