Posts Tagged ‘Microsoft’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
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Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
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Thursday, April 21st, 2016
Just as Auguste Rodin revived the art of sculpture at the end of the 19th century in Europe, and Wynton Marsalis rescued the art of jazz by the end of the 20th century in America, here in the 21st century University of Illinois CS professor Rob Rutenbar is resurrecting the art of teaching VLSI design around the world.
He’s doing that via his Coursera-based online class entitled VLSI CAD: Logic to Layout, a course with an enrollment that defies comprehension. Per Rutenbar’s own whimsy: “There are about 25,000 people working in the EDA industry today. About 55,000 of them have signed up for my class.”
I had a chance to speak by phone with Dr. Rutenbar earlier this week. He was sitting in his office in Urbana-Champaign, but looking out an academic landscape that encompasses the entire world.
[hint: a MOOC is a Massively Open Online Course.]
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Tags: Amazon, Auguste Rodin, Barnes-and-Noble, Borders, Cadence, Coursera, EDA, Google, Jeff Bezos, Massively Open Online Course, Microsoft, MOOC, Rob Rutenbar, Stanford, University of Illinois, VLSI CAD: Logic to Layout, VLSI Design, Wynton Marsalis
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Thursday, October 23rd, 2014
Dr. Pranav Ashar embodies the best of what EDA is all about these days, serving as articulate spokesman for the company’s technology, while tracking the wider view as well, the trends and future of the industry. I spoke with Dr. Ashar in early October and was impressed with his willingness to participate in an unscripted interview.
Our conversation was precipitated by Real Intent’s recent announcement of the 2014 release of its Meridian CDC product for clock-domain crossing analysis, which per the press release, adds enhanced speed, analysis and debug support for SoC and FPGA design teams, introduces a new CDC interface approach, a new way of debugging CDC violations, and a unique way to handle flat and hierarchical designs comprehensively. Dr. Ashar started our conversation by talking about the announcement.
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Tags: Apple, Bell Labs, clock-domain crossing analysis, Dr. Pranav Ashar, Facebook, Google, Meridian CDC, Microsoft, NEC Labs, Real Intent, VLSI Design
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Thursday, July 17th, 2014
Once again EDAC’s Market Statistics Service has released quarterly results for the EDA and IP industries, and once again Mentor Graphics CEO Wally Rhines has taken time to debrief the press on the numbers. When we spoke by phone on July 15th, Rhines started with a qualitative eval of the financial situation in Q1_2014, and moved from there to answer several longer-range questions about autos and today’s troubled world.
“The first quarter of 2014 was good for the industry, but not great,” he said. “With overall growth of 4.6 percent, year over year, it was a good quarter with the highlight being logic design was up a solid 6.6 percent. Other than that, there was not a lot else [remarkable in EDA].”
“Steady, but not glamorous, for Q1?” I asked.
Rhines said, “Yes, steady as she goes in EDA. The IP business, however, was up strongly in Q1, driven up by results from the non-reporting companies, not members of EDAC. We collect public info from non-reporting IP companies such as ARM, Imagination Technologies, MIPS, Rambus [and Synopsys], and we can see overall that the IP business [exhibited] 10-percent growth, quarter over quarter, Q1_2013 to Q1_2014.”
He added, “The bigger trend [visible in] the current MSS report is that all of the world is showing strong [sales], except Japan which is very weak, down 19 percent in contrast to Asia Pacific, which is up 13.5 percent.
“You should also note that North America and Europe are quite strong, up 7 percent or more. Japan is well below those regions as well. Japan used to be a big part of the total [numbers for the industry], substantially larger than the Asia Pacific Region, but now the Pac Rim is twice the size of the Japanese market.”
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Tags: ARM, Cadence, DAC, EDAC, Egypt, El Salvador, Ford, Imagination Technologies, Infineon, Israel, James Buczkowski, MathWorks, Mentor Graphics, Microsoft, MIPS, MSS, Nokia, NXP, Pakistan, Rambus, Renesas Electronics, Synopsys, TI, Wally Rhines
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Tuesday, March 18th, 2014
Agnisys exhibited at DVCon several weeks ago in Silicon Valley, but within the time constraints of the show I didn’t have a chance to talk with them. Fortunately, that was remedied at 9 am this morning – 9:30 pm in Noida – during a phone call with company CEO Anupam Bakshi, who was visiting his team in India at the time of our conversation.
Prior to his involvement with Agnisys, Bakshi served at Avid Technology, PictureTel, Blackstone Consulting Group, Cadence, and Gateway Design Automation.
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WWJD – Let’s start with the elevator pitch. In 25 words or less, when did the company start and what do you do?
Bakshi – We started 6 or 7 years ago and are Massachusetts-based, although a lot of our development is done in Noida. Our products, called IDesignSpec, focus on the area that the big EDA companies don’t, providing an executable specification tool for chip design.
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Tags: Agnisys, Amazon, Anupam Bakshi, CERN, DVCon, IDesignSpec, Mercury Computers, Microsoft, NASA, Raytheon
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Thursday, November 14th, 2013
This week in Las Vegas, Dassault Systèmes hosted one of their many global confabs where customers consult with each other about the joys of using Dassault’s product lines. At this particular conference, Panasonic’s newly launched ToughPad enjoyed special focus, featuring heavily in keynotes and on the exhibition hall floor.
The 20″ ToughPad is among the largest tablets in the history of humankind, weighing in at around 6 pounds, and comes in two versions. One’s targeted at sales folks who want to haul around a huge screen for maximizing presentation punch (and for watching movies while they’re waiting at the gate). That one sells for around $5K. The other version’s a full-on workstation, good for designing stuff, repairing helicopters (virtually), and spinning things around and around in Dassault’s 3D design software until you’re dizzy with delight. This more-powerful, badasser version will set you back around $7.5K or more, but surely it’s worth the price.
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Tags: Dassault Systemes, Las Vegas, Microsoft, Panasonic, ToughPad
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