Posts Tagged ‘Mentor Graphics’
Thursday, July 26th, 2012
We’re coming up on almost four years, full on, since the momentous events of 15 October 2008 when the entire top executive team at Cadence exited stage left.
At the time, of course, the world was paying a shade less attention to EDA, and a shade more attention to a global crisis unfolding minute-by-minute featuring household concepts such as bankruptcy, subprime mortgages, and derivatives, and household names such as Lehman Brothers, AIG, Merrill Lynch, Bank of America, Goldman Sachs, Morgan Stanley, Washington Mutual, JPMorgan, Wachovia, CitiGroup, and the FDIC, to name a few.
Meanwhile, the folks who held CDNS in mid-October 2008 were holding shares that had lost almost 80% of their value over the previous 12 months, plummeting from $20+/share to around $4/share in that time frame.
The world may have been consumed by news of the larger global meltdown in October 2008, but various CDNS shareholders were sufficiently focused on the disaster at Cadence to precipitate upwards of a dozen class-action suits against the company in protest.
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Tags: Cadence, CDNS, Denali, EDA, EDA360, Lip-bu Tan, Magma, MENT, Mentor Graphics, SNPS, Synopsys
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Thursday, July 5th, 2012
The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?
Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …
… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.
This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?
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Tags: AJ Incorvaia, Ansoft, Ansys, Apache, Cadence, CST, HSPICE, HyperLynx SI, Lightning Verify, Mentor Graphics, OrCAD, PowerSi, SI, SIgnal Integrity, Sigrity, SiSoft, Synopsys, SystemSI, TSMC, Zoltan Cendes, Zuken
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Monday, June 4th, 2012
DAC started with a boom on Sunday night, June 3rd. EDAC reports that 900 people registered for the opening reception, and by the crush of people in Salon 7 in the basement of the San Francisco Marriott Hotel, it looked like everybody showed up. [Although perhaps not quite 900…]
Setting up my word processor on a cocktail table at the back of the crowd, I manged to see numerous thought leaders in EDA as they swam by, in and out of the stream of people that swirled throughout the wine, buzz & music-laden ballroom as EDAC’s Executive Director Bob Gardner’s Jazz Trio entertained up on stage.
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Tags: #49DAC, Bob Gardner, Chris Rowen, DAC, DAC 2012, DAC 2013, Design Automation Conference, EDAC, Jennifer Cermak, Jill Jacobs, Lee Woods, Mentor Graphics, MOD Marketing, MP Associates, OpenAccess, Ry Schwark, Si2, Steve Schulz, Synopsys, Tensilica, Wally Rhines
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Wednesday, May 30th, 2012
Founded in 2000 in France, EVE has been a highly visible part of the EDA landscape for over a decade. In the week prior to the Design Automation Conference in San Francisco, I spoke by phone with Lauro Rizatti, General Manager and Marketing VP for EVA-USA, headquartered in Silicon Valley.
Lauro said that EVE is not releasing specific news at DAC because the company is launching the newest version of its ZeBu emulator in November 2012, the ZeBu-Server2 based on the Xilinx Virtex 6. Following that, EVE will be releasing the ZeBu-Server3 in mid-2014 based on the newest version of Xilinx Virtex 7. It’s not a coincidence that EVE’s hardware, built around ‘off the shelf’ FPGAs, enjoys a new release every two years.
Per Lauro: “Working with FPGAs, we don’t have to wait for internal, custom chip development to move forward. And because we use Xilinx, we ride their technology road map. Every 2 years they launch a new platform, and every 2 years so does Eve. We think we have a brilliant strategy, and the results can be seen in our earnings. We recognized $52 million revenue and $62 million in bookings over the last 12 months.”
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Tags: Cadence, DAC 2012, Emulation, EVE, EVE-USA, Lauro Rizatti, Mentor Graphics, TI OMAP 5430, Xilinx Virtex 6, Xilinx Virtex 7, ZeBu-Server2, ZeBu-Server3
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Wednesday, May 16th, 2012
 On May 1st, Joe Costello was standing in his office at Orb Networks on the 6th floor of a building in downtown Oakland. When we started our phone call, he said, “I’m looking down on Broadway and there’s a massive march out there. It’s crazy — wish I could send you the video!”
It was, of course, the May Day Occupy Oakland march, which seemed just about right for this long-planned interview.
Twenty years ago, Joe Costello was CEO at Cadence; today he’s President & CEO at Orb Networks, a company that’s “cranking away at cool stuff in the media space.” Twenty years ago, Joe Costello was the epicenter of EDA; today he’s roiling things up elsewhere in the technology ecosystem.
So first we talked about Joe’s present and future, and then we got around to EDA’s present and future and What Would Joe Do if he was back in the epicenter today.
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Tags: Cadence, EDA, EDA investment, Joe Costello, Lucio Lanza, Mentor Graphics, Oasys Design Systems, Orb Networks, Synopsys
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Sunday, May 13th, 2012
DAC looms!
 If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.
Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.
After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:
* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel
If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.
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Tags: ACM Sigda, Brad Heaney, DAC, Design Automation Conference, Duolos, EDAC Enterprise Licensing Conference, Gabe Moretti, IBM, Intel, Kathryn Kranen, Lucio Lanza, Mentor Graphics, North American SystemC Users Group Meeting, Oski, Paul McLellan, Red's Java House, Samsung, Tom Halfhill
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Thursday, May 3rd, 2012
The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.
Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.
In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.
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Tags: Antibes, ARM, Broadcom, Cadence, Cezanne, France, HP, IBM, Infineon, Intel, Matisse, Mentor Graphics, Nice, Picasso, SAME, Sophia Antipolis Microelectronics Forum, STMicro, Synopsys
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Wednesday, April 25th, 2012
When you think of Forte, think of the shopping mall – because just as Macy’s and Nordstrom’s are anchor tenants in your local mall, Forte Design Systems is the anchor tenant in the ESL mall.
 Also when you think of Forte, think of Brett Cline. Brett’s been the face of the company for many a year, and continues to address with palpable enthusiasm the past, present, and future of everything having to do with the ESL – Forte and the system-level design shopping mall within which the company functions.
Last month, here in What Would Joe Do, Calypto had center stage speaking about their recent acquisition of the Catapult C high-level synthesis tool from Mentor Graphics.
This month, Forte has center stage by way of Brett’s response to Calypto. When we spoke by phone this week, Brett began by countering Calypto VP Shawn McCloud’s comment that Forte is in trouble.
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Tags: Brett Cline, Cadence, Calypto, ESL, Forte, Forte Design Systems, Mentor Graphics
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Tuesday, April 24th, 2012
There’s good news and bad news, in my opinion, with regards to Rajeev Madhavan, founder and CEO of Magma Design Automation, a company that was acquired by Synopsys on February 22, 2012.
The good news it that Rajeev is available to the press for candid interviews like the one included below. The bad news is Rajeev is not going to be part of the EDA landscape as he explores various options for the next phase of his life – and that means the industry will be just that much less interesting, at least for a while.
We spoke by phone in late February.
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Peggy: Hey, Rajeev, how are you doing?
Rajeev: I’m doing pretty much okay as I think about what’s next. I’ve got opportunities, and I’ve got other interests I can now pursue – most people rarely get this kind of opportunity in life, so I’m grateful.
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Tags: Aart de Geus, Andy Bechtolsheim, Cadence, EDA, Intel, M&A, Magma, Magma Design Automation, Mentor Graphics, Rajeev Madhavan, Synopsys, TSMC, Wally Rhines, Wind River
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Saturday, March 24th, 2012
When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool – it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”
Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:
 Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.
Q: Who’s the competition?
Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.
Q: Your exit strategy?
Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.
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Tags: Apache, Atrenta, C-to-RTL, Calypto Design Systems, Catapult C, Equivalence Checking, Forte, HLS, LaunchM, Mentor Graphics, PowerPro, RTL-to-RTL, Shawn McCloud, SLEC
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