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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

DAC 2012: Wicked Wednesday in San Francisco

May 13th, 2012 by Peggy Aycinena

DAC looms!

If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.

Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.

After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:

* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel

If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.

Once you’re in the Exhibit Hall, you can also dash by the Pavilion Panel stage.

There you’ll find Lucio Lanza leading the discussion about how to get the costs we pay for our electronic clutter to be more representative of what it costs to make it [in other words, get the customer to pay more!], Paul McLellan’s panel will be making physical design better, Tom Halfhill’s panel will be creating better embedded design methodologies, Kathryn Kranen’s high school students will be profiling their lives in technology, and Gabe Moretti’s panel will be making or buying stuff for hardware-assisted prototyping and verification.

If nothing you’ve seen here so far meets your needs, however, also on Wednesday there’s the all-day EDAC Enterprise Licensing Conference, the North American SystemC Users Group Meeting, and the Duolos-sponsored workshop on UVM.

So really, what’s so wicked about Wednesday? In fact, the real meat of the day will not be found in these high-level chit chats, panel discussions, or keynotes. Most of that content, although informative, provides more of a nuanced kind of learning for the folks who come to DAC.

In fact, the real knowledge harvesting at DAC comes from attending the paper sessions in various meeting rooms scattered throughout the ginormous Moscone Center. There, you’ll find all of this and more …

Routing-driven design closure, Non-volatility in computing, Discussion on error resilience and imprecise hardware [not necessarily in that order], “Xterminating” bugs through verification and test, Analog optimization and design, The future of IC reliability in embedded systems, Adaptive computing, The power-performance tradeoff, and How to Apply EDA Techniques to Broader Applications in the area of Bio Design Automation.

In other words, if you really want the intellectual challenge that DAC offers, if you want to learn something that real engineers need to know, you should be attending the paper sessions on Wednesday because that’s when the wicked stuff at DAC is going to be center stage for those smart enough to be in the room.

Wicked, which starts with W, which also stands for Wise.

And, you’ll especially be among the wise if you head out from Moscone Center and stroll down to Red’s Java House along the Embarcadero sometime during the day on Wednesday.

It’s a San Francisco landmark that serves up coffee, beer, fish & chips, and the best view of the Bay Bridge from anywhere in The City. See you there.


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