Posts Tagged ‘DesignCon’
Thursday, February 9th, 2017
Thanks to the staff of EDACafe, yet more video interviews are now available on the website. This content, recorded at last week’s DesignCon, continues to capture the technical expertise of those who pursue market excellence with today’s technology.
Those interviewed include: TE Connectivity’s Nathan Tracy, Rambus’ Mohit Gupta, Anritsu’s Joe Mallon, CST’s Klaus Krohne, Keysight Technologies’ Stephen Slater, DVT Solutions’ Brian Shumaker and Signal Microwave’s Bill Rosas, Mentor’s Dave Kohlmeier, ESD Alliance’s Bob Smith, Cadence’s Sam Chitwood, and Asteelflash’s Matheiu Kury.
You can see all of the DesignCon 2017 videos here.
Also of interest this year at DesignCon in Santa Clara, Steve Yamaguma was the winner of the Amazon Echo offered in a raffle in the EDACafe booth at the show.
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Tags: Bill Rosas, Bob Smith, Brian Shumaker, Dave Kohlmeier, DesignCon, Joe Mallon, Klaus Krohne, Matheiu Kury, Mohit Gupta, Nathan Tracy, Sam Chitwood, Sanjay Gangal, Stephen Slater, Steve Yamaguma
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Thursday, December 15th, 2016
The New Year promises to be a dramatic one on many fronts, not the least being the ever-quickening pace of change in technology. Evidenced by the continued and enthusiastic attendance at conferences around the world, there are clearly so many opportunities to network, learn, and develop sales leads at these events. Bets are on that you’ll be attending at least one of these. Happy New Year!
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* CES2017: Consumer Electronics Show – January 5-8 – Las Vegas
No one need tell you what CES encompasses: Here in its 50th annual edition, it will include everything. The 2017 keynotes will include addresses from the CEOs of Qualcomm, Huawai, Nissan Motors, and Nvidia. But the topics covered in this massive 100,000-attendee show will cover cars, wearables, healthcare devices, and every conceivable type of consumer clutter.
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Tags: CAR-ELE, CDNLive, CES, DAC, DesignCon, DVCon, Mobile World Congress, Phil Kaufman Award Dinner, SNUG
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Thursday, August 28th, 2014
With the advent of September, the fall conference season begins. Here are some upcoming meetings you may want to attend.
* DesignCon China – September 2-5 – Shenzhen
Last year close to 13,000 attended ICC-China. Expect even more to attend this year.
* Mentor Graphics Forum – September 3 & 5 – Shanghai & Beijing
Keynote will be given by Mentor CEO Dr. Wally Rhines, followed by President of ARM Greater China Allen Wu talking about the next 10 billion chips to be manufactured in China.
* IDF14: Intel Developers Forum – September 9-11 – San Francisco
Intel CEO Brain Krzanich will give opening keynote, followed by lots of talk about the IoT.
* PCB West 2014 – September 9-11 – Santa Clara
The most important conference of the year for board designers.
* Mentor U2U Automotive – September 10 – Dearborn
The debut of a new Mentor User2User event focusing on one of Mentor’s favorite core competencies.
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Tags: ARM TechCon, DesignCon, DVCon, ICC-China, ICCAD, IDF14, MemCon, Mentor U2U, PCB West, SNUG, TSMC OIP
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Thursday, January 9th, 2014
The New Year has arrived and with it a chance to reset the calendar for 2014. Following are only some of the conferences on the horizon. It’s interesting to look closely at the list to see which conferences are in direct scheduling conflict with each other.
* ASP-DAC 2014
Asia & South Pacific Design Automation Conference
Singapore – January 20-23
* DesignCon 2014
“Where the Chip Meets the Board”
Santa Clara – January 28-31
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Tags: ASP-DAC, CDNLive, DAC, DATE, DesignCon, DVCon, EmbeddedWorld, ISQED, Mobile World Congress, SPIE Photonics
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Monday, February 4th, 2013
Breker Verification Systems VP Tom Anderson presented a concise tutorial on low-power SOC verification at DesignCon on January 30th. He began by laying out the challenges of low-power design, with an eye to the verification problems associated with various strategies:
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Low-power SOC verification …
The need for low-power design is ubiquitous, with today’s plethora of consumer devices being battery-powered. ‘Big iron’ machines in modern data centers are also driving the need for low-power chips. As well, governments worldwide – especially in Europe – are passing ‘green’ laws; if you’re building a ‘big iron’ class of machine, you may be required by law to meet specified power limits.
There are various techniques emerging to meet these needs. Circuit-level design strategies include special transistor and cell design for non-critical paths. Different voltage thresholds are also an option, yielding a variety of performance levels and power consumption at different points on-chip; designers can make a one-time trade-off between performance level and path options on-chip. These techniques have little or no impact on functional verification. Other strategies, however, do.
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Tags: Breker Verification Systems, DesignCon, Low-power SoC verification, Tom Anderson
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Thursday, December 6th, 2012
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
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Tags: Altera, ARM TechCon, Blue Pearl, DATE, DesignCon, Grey Cell Methodology, RTL Signoff for FPGAs, SAME, Shakeel Jeeawoody, SNUG, Synopsys, Synplicity, Xilinx
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