Posts Tagged ‘Cadence’
Wednesday, June 5th, 2013
The last day of the Exhibit Hall portion of DAC always arrives with a certain sensibility. Over the course of the 3 days, the place has become something between Our Town and a small college campus, and now with graduation it’s not clear when everyone will be together again. Yet the next phase of life beckons with all of its possibilities and trepidations, and people have to move on.
Happily this afternoon, as the 50th instantiation of DAC drew to a close in Austin, many residents of Our Town EDA could look forward to continuing the camaraderie at a first-ever DAC Banquet this evening at the nearby Four Seasons Hotel. Many of us were en route home by that time by plane, train or automobile and could not be there, but I hear tell it was a great evening. So my Top 10 on Day 3 in Austin starts with this late night report regarding the banquet thanks to ARM’s Tiffany Sparks, who was in attendance at the event.
(more…)
Tags: Analog System Design, Bagpipes, Bill Joyner, Brett Cline, Cadence, Carlo Tinella, CAST, Chris Rowen, DAC, Design Automation Conference, DOCEA, Flexras, Forte, Garrison Hefter, Gene Matter, Gunnar Scholl, Hal Barbour, Hayder Mrbet, Jasper, Kathryn Kranen, Landon Hegedus, Leon Stok, Niteka Raina, Our Town, Pat Pistilli, ProDesign, Rick Perry, Rob Rutenbar, Tensilica, Tiffany Sparks
No Comments »
Thursday, May 30th, 2013
In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.
At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.
In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”
It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.
(more…)
Tags: ATopTech, Bijan Kiani, Cadence, DAC 2013, DAC Global Forum, GlobalFoundries, Jue-Hsien Chern, Mentor Graphics, Michael Buehler-Garcia, Ping Hsu, Suk Lee, Synopsys, TSMC, TSMC FinFET v0.1
No Comments »
Thursday, May 23rd, 2013
BDA chief operating office Paul Estrada has been at Berkeley Design Automation for over 7 years and is as enthused about the company today as when he first arrived. Particularly, because he says BDA is getting more attention than ever these days thanks to its growing portfolio of leading-edge products.
“We are a small business that continues to grow,” Estrada says with pride, “focusing on nanometer verification, a market where there are lots of problems, but where we are definitely making [inroads]. It’s an area that’s ripe for innovation, and better tooling, and as we don’t see the big EDA companies putting time or effort into making progress there, it’s a sweet spot in the market for us.”
Sounds great, so what’s the elevator pitch for potential customers?
Estrada responds easily: “Many companies continue to buy from our competition – principally Cadence and Synopsys – but we go into leading edge RF and analog/mixed-signal design teams and ask them what they can’t do with their current tools. They tell us and then we do those things for them with our tools. As a result, they buy even more tools from us and we go on from there.
(more…)
Tags: 0-In Design Automation, ACE, Analog Characterization Environment, Analog FastSPICE, BDA, Berkeley Design Automation, Cadence, Mentor Graphics, Paul Estrada, Ravi Subramanian, Synopsys
No Comments »
Thursday, May 16th, 2013
Privately-held Calypto is on quite a clip these days, with developments at the company being closely followed by the press. That’s not completely surprising given that a new CEO came on board earlier this year, Sanjiv Kaul, and a new VP of Applications Engineering was named just this week, Thomas Bollaert being promoted into that role. I had a chance to speak with CEO Kaul recently. Following is a snapshot of that conversation.
(more…)
Tags: Cadence, Calypto, Catapult, Forte, high-level synthesis, HLS, Mentor Graphics, Sanjiv Kaul, Synopsys, Thomas Bollaert
No Comments »
Wednesday, May 1st, 2013
Joe Costello came to town tonight and wowed his acolytes.
 Thanks to EDAC, Kathryn Kranen, Steve Pollock, Bob Gardner, Jennifer Cermak, Jill Jacobs, Gloria Nichols, and Cadence – Jim Hogan hosted Costello on stage at Cadence’s San Jose Headquarters for a 90-minute event that was one part Reunion Tour [lotsa Cadence alums in the audience in addition to the two on stage], one part Pity Party for Mentor Joe & Mentor Jim [oh so many visits to VCs who failed to embrace a startup’s pitch], and one part Brag Fest for VC Joe & VC Jim [oh so many visits from potential startups whose pitch we simply could not embrace].
Add up those parts and you’ve still only got half of the content of tonight’s event; the other half of the Joe Costello Love-in consisted of a detailed Lesson in Rhetoric. Perhaps not surprising, given that the event was titled: Joe Costello Shares His Secrets for Communicating a Compelling Company Story. What is surprising is how closely Costello’s advice to his adoring audience mirrored Cicero’s Five Canons of Rhetoric.
(more…)
Tags: Bob Gardner, Cadence, Canons of Rhetoric, Cicero, EDAC, Gloria Nichols, Jennifer Cermak, Jill Jacobs, Jim Hogan, Joe Costello, Kathryn Kranen, Steve Pollock
No Comments »
Thursday, April 4th, 2013
Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.
Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.
(more…)
Tags: Adapt-IP, Alcatel-Lucent, Aparna Dey, ARM, Brandon Wang, Cadence, Camille Kokosaki, Dan Nenni, Docea Power, Don MacMillen, Dusan Petranovic, E-System Design, eda2asic, EDPS 2013, Frank Schirrmeister, Gary Smith, Gene Jakubowski, Gene Matter, Gregory Wright, Guy Bois, Herb Reiter, Intel, Ivo Bolsens, James Colgan, John Heilein, John Swan, Kiron Pai, Luigi Capodieci GlobalFoundries, Mentor Graphics, Michael McNamara, Micron, Mike Black, Namraj Nandra, Naresh Sehgal, Net App, Nimbic, Oracle, Raymond Leune, Rob Aitken, SemiWiki, Space Codesign, Srinivas Nori, Srinivasa Banna, Synopsys, Tom Dillinger, Tom Quan, TSMC, Xilinx, Xuropa
No Comments »
Thursday, March 21st, 2013
It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.
 Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.
In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.
(more…)
Tags: ARM Connected Community, Cadence, DAC 2013, DAC Exhibit Hall, DAC Innovation Square, GlobalFoundries, Synopsys, TSMC
No Comments »
Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
(more…)
Tags: 14nm FinFET, Aart de Geus, Ansys, Apple, ARM, Cadence, Computer History Museum, DAC, DATE, DoubleTree, EDA Reunion, EUV, Google, Gordon Moore, Jasper Design Automation, Jim Hogan, Joe Costello, Kathryn Kranen, Lip-bu Tan, Mentor Graphics, MOD Marketing, Nimbic, OCP-IP, Raul Camposano, Rich Valera, Samsung, Simon Segars, Synopsys, Wally Rhines
2 Comments »
Thursday, February 28th, 2013
Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”
Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.
(more…)
Tags: Ambar Sarkar, Cadence, DVCon 2013, Jason Sprott, John Brennan, Maxim, Meirav Nitzan, Mike Stellfox, Neyaz Khan, Oski Technology, ParadigmWorks, Verification Planning, Verilab, Vigyan Singhal, Xilinx
No Comments »
Thursday, February 21st, 2013
You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.
If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.
(more…)
Tags: Accellera Systems Initiative, Cadence, DVCon 2013, Free Lunch, Harry Foster, John Brennan, Mentor Graphics, Synopsys, Wilson Research Group Functional Verification Study, Yatin Trivedi
No Comments »
|
