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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Sanjiv Kaul: Calypto and HLS to seize the day

May 16th, 2013 by Peggy Aycinena

Privately-held Calypto is on quite a clip these days, with developments at the company being closely followed by the press. That’s not completely surprising given that a new CEO came on board earlier this year, Sanjiv Kaul, and a new VP of Applications Engineering was named just this week, Thomas Bollaert being promoted into that role. I had a chance to speak with CEO Kaul recently. Following is a snapshot of that conversation.


WWJD – What brought you to this job?

Sanjiv Kaul – I’ve been watching the company for quite a while, ever since it was formed, and the timing was right this year for me to join. I’m very excited about the technology, because high-level synthesis is finally going mainstream. It’s crossing the chasm at last, as the biggest customers out there are seriously putting plans in place to deploy high-level synthesis across many of their designs.

Also, of all of the companies working in this area, Calypto is best positioned to win in the marketplace. It has high-level verification and power optimization technology to produce power-optimized RTL automatically. Calypto presents a unique value proposition; the timing for success is right now.

WWJD – The company’s had an exciting year so far. What are the plans for next year to keep things clipping along?

Sanjiv Kaul – In the next year or so we will become the vendor of choice for many of the big companies making the decision to deploy high-level synthesis.

WWJD – Who are you competing against in this area?

Sanjiv Kaul – There are two companies in the high-level synthesis space. One is Forte Design and the other one is obviously Cadence.

WWJD – And how does Calypto stack up against those guys?

Sanjiv Kaul – We compete well against both of them, because our high-level synthesis technology is Catapult, which comes from Mentor Graphics. Calypto started off as a company creating sequential logic analysis, a tough technology sector, so most people didn’t give the company a chance to get it done. Our success now is dependent on the high-level synthesis market taking off, which it is!

The other thing to realize is, for a formal tool to do really well it needs to get suggestions from the high-level synthesis product about how the design is being implemented. That’s why the Catapult technology was spun out of Mentor and became part of Calypto. With us, it now has a unique opportunity to succeed, because part of our technology offering is deep sequential analysis – the best in the marketplace – and that [dovetails well] with Catapult.

WWJD – Given the opportunities in high-level synthesis you describe, would it ever make sense for Mentor to buy Calypto, to take the Catapult technology back inside?

Sanjiv Kaul – It would be up to them if they thought to do that, or perhaps they’ll be happy to see it move up on its own. A product like this takes time to go mainstream, because it’s very hard to pay attention to it in the way it deserves.

WWJD – Why didn’t Mentor keep the technology inside? Surely they had the bandwidth to ‘pay attention to it’ inside their own firewall.

Sanjiv Kaul – Well, there’s a lot more to ESL than just high-level synthesis, which means taking C or SystemC and outputting RTL. The rational given by Mentor when they spun out Catapult was the synergy between Calypto’s SLEC and Catapult C high-level synthesis. Also, making this market happen and making it into something really big are two different things.

WWJD – What about Calypto merging with Forte Design? Could you ever see that as a possibility?

Sanjiv Kaul – We wouldn’t go on record talking about a merger with any other company.

WWJD – Where was the Catapult team located prior to Calypto, and where is the team located now?

Sanjiv Kaul – Before, it was in Wilsonville and now it’s in Wilsonville, San Jose, and Noida. Over time, we’ve had people in all three locations. As with every company, you go where the talent is, you hire the talent there, and you develop it across multiple technologies.

WWJD – How does high-level synthesis verification work?

Sanjiv Kaul – We are verifying C to RTL by formal techniques; it’s similar to the kind of technology in the marketplace which is RTL to netlist. A lot of the equivalence checkers or formal tools that exist are RTL to netlist/gates, but we allow you to verify C code to RTL, RTL to RTL, C to C.

In order to do this, you need to do deep sequential analysis, but that’s not an easy problem, to look at multiple clocks. Not all clock cycles are created equal, so how do you know you’re comparing apples to apples? At a higher level of abstraction, you need to look at multiple clock cycles to draw the equivalence.

WWJD – This is all seems somewhat convoluted. How do you know when you’re done verifying?

Sanjiv Kaul – From a verification point of view, basically the tool will come back and say, ‘These two designs are equivalent.’ When the tool comes back and says, ‘They’re not equivalent,’ then you’ve got a problem.

WWJD – Isn’t it easier to do that at the RTL level?

Sanjiv Kaul – There are multiple reasons why people design at the C level. First, chips are getting very complex, [which is why] many people see RTL as the new netlist; 25 year ago, people moved to RTL to deal with the complexity of that time.

Now that chips are larger, part of the strategy [to deal with the complexity] has been to use IP and design reuse with large pieces of the chip coming from outside the team. There’s just more and more to be designed, especially blocks that are very algorithmic – things like image processing and audio processing, all of which are very algorithmic – and C is a good way to come up with the right algorithms to meet those design needs, and to pick the one that’s best. Many people who are designing these blocks are doing it in C.

WWJD – You sound very confident about all of this. What technical milestones are on your roadmap to continue progress here?

Sanjiv Kaul – When we did the merger with the Catapult team, we delivered on the first level of integration. Going forward, we will deliver even deeper integration.

WWJD – Meaning what, specifically?

Sanjiv Kaul – Meaning there will be much tighter integration over a wider variety of designs.

WWJD – Who at Calypto is responsible for overseeing the technical roadmap?

Sanjiv Kaul – The R&D team looks at the technical roadmap, but it’s a collaboration between the Applications team, R&D, and Marketing, all constantly looking at what’s changing in the marketplace.

Of course, R&D does need time to develop a major release, but as they are working on that release, they’re planning at the same time for the release that comes after that on. It’s an ongoing process whenever you have scheduled releases – keeping an eye on what customers are demanding, where the competition is going, and where you think the next opportunity will be.

WWJD – How does your new role as CEO at Calypto relate to your earlier experiences in EDA?

Sanjiv Kaul – I have always been attracted to discontinuities in the marketplace.

I spent 10 years at Synopsys; the first product I was involved with there was PrimeTime. When we were looking to roll the product out, the whole static timing market was only five or six million dollars, but we felt the time for static timing sign-off was ready. Today, PrimeTime is an over-$100 million business and is the sign-off engine of choice.

Later, when I was General Manager/Vice President of the implementation unit at Synopsys, the important question was how to reach closure between synthesis and physical design. I always felt that we needed to bring place-and-route and timing together; Physical Compiler was a [huge success in the marketplace] from its very first year.

Today, I have a similar feeling that this is the time for high-level synthesis. As I said, I am very excited to be at Calypto as this technology goes mainstream in the marketplace.


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