Posts Tagged ‘Atrenta’
Thursday, August 11th, 2016
It takes courage to re-launch an existing product rather than start from scratch, to announce a refreshed and updated offering as if it were something brand new. That’s certainly the case with Synopsys‘ recent release of TetraMAX II. It took courage to build on a franchise that first arrived on the scene not just in the last century, but in the last millennium.
And it was with this sentiment that Synopsys’ Robert Ruiz and I started a recent phone call to discuss the July news that TetraMAX II has arrived on the scene.
Ruiz began: “This is TetraMax II. We wrote the key engines from scratch, an effort that took the R&D team a full two years to complete. The goal was to get 10x faster and 25-percent fewer patterns.”
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Tags: ATPG, Atrenta, BIST, Robert Ruiz, SNUG, STMicro, Synopsys, TetraMAX II, Virage Logic
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Thursday, March 10th, 2016
You would probably have learned more about Ajoy Bose by reading his biography than by attending Jim Hogan’s gentle exercise in collegiality on Tuesday night, March 1st, in Silicon Valley. The conversation between these two giants of EDA, hosted by EDAC as part of DVCon week, was consistently unstructured, whimsical and seemingly without outline.
The next day, I sat in a coffee shop and struggled to find a handle with which to write a coherent summary of the previous night’s random access memory album. But that handle would not reveal itself.
Then I happened to glance over to a nearby table where another caffeine addict was buried in a book: The Man Behind the Microchip. I asked the addict who exactly was the subject of the book and the answer came back: Robert Noyce.
So Robert Noyce is the man behind the microchip, I pondered. The only man behind the microchip? Like Steve Jobs invented the iPod/iPad/iPhone? Or Thomas Edison invented the electric light?
No wonder, I realized, it was hard to get a handle on the previous night’s Hogan/Bose interview. They didn’t do anything. Robert Noyce did it all. And without help. Hogan and Bose did nothing, and ergo had nothing to offer their audience.
These two were not part of a vast conspiracy of contributors, all adding their particular drips and drops of innovation into the trickle of technology, that rolled into a small creek of creativity, that ran into a moderate-sized stream of science-turned-engineering, which poured into a roaring river of real change, which crashed into a seething sea of twenty-first century digital life.
Of course, that’s nonsense. Robert Noyce did not do everything, and Hogan and Bose did not do nothing.
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Tags: Ajoy Bose, Atrenta, Bell Labs, Cadence, Dallas Cowboys, DVCon, EDAC, Gateway Design Automation, Graham Bell, Hermann Gummel, IIT, India, Interra, Jim Hogan, John Bardeen, Jon Gertner, Larry Nagler, Leslie Berlin, Levy Stadium, Mike Hackworth, Robert Noyce, Roger Staubach, Silicon Valley, Spyglass, Steve Jobs, Steve Szygenda, Synopsys, Thomas Edison, UT Austin, William Shockley
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Wednesday, February 10th, 2016
Sometimes you just gotta wonder what happens behind the closed doors of the executive suite. Last June, when Synopsys acquired Atrenta, Atrenta’s founder – a distinguished technologist, alum of IIT Kanpur, UT Austin, Bell Labs, Cadence and Interra, and profoundly well-seasoned EDA leader – closed the door on his leadership role at the company he founded 14 years before.
I will admit, I do not know if Dr. Ajoy Bose actually ever reported to duty at Synopsys last summer – the received wisdom would have us believe he needed to set foot there long enough to help his team transition into the Big Purple – but in truth, it is hard to imagine him ever playing second fiddle to Dr. Aart de Geus or Dr. Chi-Foon Chan, or anyone else for that matter. He is a man of that much dignity and gravitas.
Of course, if Bose did punch a time clock at Synopsys, it was for nary a nanosecond in geologic time. It’s been 9 months since the acquisition and now Bose is clearly free to speak in public about the past, present and future of the industry he has helped to create. That surely would not be happening if Bose was just a node in the org chart that has Chan and de Geus at the top of the pyramid.
So there’s one half of the good news included herein.
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Tags: Aart de Geus, Ajoy Bose, Atrenta, Bell Labs, Cadence, Chi-Foon Chan, DVCon, EDAC, Interra, Jim Hogan, Synopsys
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Sunday, June 7th, 2015
Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.
So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:
10 — Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)
9 — EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!
8 — Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.
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Tags: Ajoy Bose, Alain Labat, Anne Cirkel, Ansys, Apple, Atrenta, Cadence, DA Summer School, DAC, Design Automation Conference, EDAC, edaForum, Elliot Garbus, Fiat Chrysler Automotive, Four Seasons, Harvest Management Partners, IEEE, Intel, Karen Bartleson, Klauss Busse, Mentor Automotive, Mentor Graphics, Patrick Groenveld, Philip Wong, Soha Hassoun, Synopsys, Wally Rhines, WWDC15
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Thursday, May 29th, 2014
Like a phoenix rising from too-early reports of a reduced participation in life, the legendary Gary Smith has created a schedule of appearances at the 51st Design Automation Conference in San Francisco that would fell a man half his age. Every time you turn around at Moscone Center next week, or the Intercontinental Hotel before that, you’ll be face-to-face with events featuring the Guru Extraordinaire of EDA.
Sunday evening from 5:00 pm to 5:30 pm, Gary will yet again ring the opening bell at DAC, this year in Ballroom A of the Intercontinental Hotel across the street from Moscone. I’m putting good money on a bet that Gary will be on stage there in his best Tropical Whites, accompanied by slides, predictions, and previews of the Next Epoch in EDA and his Pavilion Panel the next day.
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Tags: 51st Design Automation Conference, Amit Gupta, Anirudh Devgan, ARM, Atrenta, Barnard Murphy, Bob Gardner, Cadence, CLK Design Automation, DAC, DAC 2014, Dead Drako, DeepChip, EDAC, Frank Schirrmeister, Gary Smith, Gloria Nichols, IC Manage, Isadore Katz, Jim Hogan, Joe Sawicki, John Cooley, Lori Kate Smith, Mentor Graphics, Moscone Center, Prince of Wales, Randy Smith, San Francisco Intercontinental Hotel, Solido Design Automation, Sonics, Vista Ventures
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Thursday, September 26th, 2013
A Professor, a Sage, and a Guru walked into a bar. Brian the Bartender, greeted them: “What’ll it be, boys?”
The Professor said, “We need some help, Brian, settling an argument.”
“No problema,” Brian the Bartender said. “I’ve got an answer for everything.”
“Well,” the Professor said, “I think ESL’s not going to happen in our lifetime, but the Guru here says it’s just around the corner now that he and his have finally got all the pieces of the flow in place.”
Brian the Bartender laughed, “Yeah, the Guru’s been saying that since the dawn of mankind!”
“Exactly,” the Professor said.
Again Brian the Bartender laughed, “Guru, can you defend yourself? And don’t even think about plunking your wordy White Paper down on the bar. This is a public house, not a public library.”
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Tags: Apache, ARM, Atrenta, Cadence, Cadence System-to-Silicon Verification Summit, Calypto, DOCEA, Duolog, ESL, Forte, Green Hills, Imperas, Intel, Jasper, MathWorks, Mentor Graphics, NVIDIA, Oasys, OneSpin, Real Intent, Synopsys, Verification, Wind River
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Thursday, June 27th, 2013
Atrenta VP Mike Gianfagna graciously extended an invitation to attend an event this evening in Grenoble, France. Jointly sponsored by CEA-Leti and Atrenta, Mike said the event was to be held on the CEA-Leti campus “in conjunction with Leti Innovations Days” and would “toast the progress Atrenta has made at its R&D facility in the city.”
It would have been great to have been there, as I was in Grenoble back in March 2011 when Atrenta first inaugurated its R&D center at the Micro and Nanotechnologies Innovation Center (MINATEC) in the city. The 2011 event was marked by a wonderful wine-enriched reception and a series of speakers articulating Atrenta’s vision in partnering with MINATEC. Those speakers included Atrenta CEO Ajoy Bose and STMicro’s Executive Vice President Philippe Magarshack, among others. You can see my original 2011 post below for more details.
Alternatively, if you want to know more about this evening’s reception in Grenoble, I have cut-and-pasted Mike Giafagna’s notes immediately below that he sent summarizing the event after the fact. It was not surprising to learn that Ajoy Bose spoke this evening, but to learn that Philippe Magarshack was also there, as he was in 2011, gives pause.
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Tags: AEPI, Ahmed Amine Jerraya, Ajoy Bose, Alain Cottalorda, Atrenta, CEA-Leti, Christian Pichoud, Geneviève Fioraso, Grenoble, Grenoble Cluster, Grenoble-Isère, Jean-René Lèquepeys, Leti Innovations Days, Loïc Liétar, Mike Gianfagna, Minalogic, MINATEC, Minatec Enterprises, Philippe Magarshack, STMicro, Thierry Collette
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Wednesday, June 20th, 2012
The news crossed the wires at 8:00 am this morning: Atrenta announced it has acquired NextOp Software, “allowing Atrenta to expand its de-facto standard SpyGlass RTL platform to include functional verification using NextOp’s patented dynamic assertion synthesis technology, and creating a more complete SoC Realization platform.” Financial terms of the transaction were not disclosed.
With the acquisition, NextOp President & CEO Dr. Yunshan Zhu becomes VP of New Technologies reporting to Atrenta Chairman, President & CEO Dr. Ajoy Bose. NextOp Co-founder & CTO Dr. Yuan Lu becomes Chief Verification Architect reporting to Zhu.
EDA luminary Jim Hogan is quoted in today’s Press Release: “I’m glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
I spoke by phone with Ajoy Bose and Yunshan Zhu earlier in the week about the upcoming announcement.
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Tags: Ajoy Bose, Assertion synthesis, Atrenta, EDA M&A, Functional verification, Jim Hogan, NextOp Software, SoC Realization, Yuan Lu, Yunshan Zhu
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Tuesday, May 8th, 2012
DAC looms!
 And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.
First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.
Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.
This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.
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Tags: ACM, Applied Micro, ARM, Atrenta, Brian Fuller, Cadence, CEDA, Chevy Volt, Cisco, DAC, Design Automation Conference, IPL Alliance, Jim Hogan, Jim Solomon, LSI, Mark Horowitz, McKormick & Kuletos', Mike Muller, PMC-Sierra, Realtek, STMicro, Synopsys, Xilinx, Yervant Zorian
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Saturday, March 24th, 2012
When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool – it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”
Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:
 Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.
Q: Who’s the competition?
Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.
Q: Your exit strategy?
Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.
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Tags: Apache, Atrenta, C-to-RTL, Calypto Design Systems, Catapult C, Equivalence Checking, Forte, HLS, LaunchM, Mentor Graphics, PowerPro, RTL-to-RTL, Shawn McCloud, SLEC
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