Archive for the ‘Uncategorized’ Category
Thursday, March 23rd, 2017
Something historic and poignant is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.
The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.
The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.
Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.
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Tags: Aart de Geus, Abu Dhabi, ARM, Brexit, Cadence, Charles Crocker, China, Collis P. Huntington, Ed Sperling, EDA, EDA 360, Egypt, ESD Allicance, Germany, GlobalFoundries, India, Japan, Leland Stanford, Lip-bu Tan, Mark Hopkins, Mentor Graphics, Pakistan, Russia, Saudia Arabia, Semiconductor Engineering, Siemens, Simon Segars, SoftBank, Synopsys, Taiwan, TSMC, U.S., UK, Wally Rhines
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Thursday, March 9th, 2017
This is a simple post with just two messages. First, EDA is hiring. All over the globe. Mentor Graphics lists over 200 openings, Cadence has almost 300 openings, and Synopsys has a staggering 900+ openings worldwide.
Of course, EDACafe’s own Mark Gilbert could have told you this. It wasn’t necessary to scour the websites of the Big Three in EDA to learn about the many jobs currently available in the industry, most for software developers, not surprisingly.
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Tags: Cadence, Larry Disenhof, Mark Gilbert, Mentor Graphics, Russia, Synopsys
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Thursday, March 2nd, 2017
DVCon generates a lot of respect, and for good reason. Engineers have attended this conference for over 25 years to further refine their skills in the area of design and verification. Yet, there’s a problem in paradise.
In an industry like EDA that’s super dominated by just three players, there’s little if any room in the industry – or at a conference like DVCon – to showcase the ideas and innovations of the Small Guys. The Big Guys teach tutorials and present papers; the Small Guys get to hang posters in the hallways.
All of that was supposed to change tonight thanks to the sponsorship of the ESD Alliance and OneSpin Solutions, as well as Vista Ventures’ Jim Hogan.
Tonight, six of the Small Guys in verification appeared on a panel moderated by Hogan hoping to get their 60-minute shot at fame. A post-Happy-Hour hour in which to lay out their case for customers to come and sample the kind of innovation that everyone knows is the watchword of technology startups, particularly in EDA.
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Tags: Adnan Hamid, Andy Stein, Avery Design Systems, Breker Verification Systems, Charles Darwin, DVCon 2017, ESD Alliance, Jim Hogan, Montana Design, OneSpin Solutions, Phil Moorby, Prakash Narain, Raik Brinkmann, Real Intent, Rick Carlson, Steve Alvin, Verific Design Automation
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Thursday, February 23rd, 2017
Accellera has just announced that Lu Dai, Senior Director of Engineering at Qualcomm, is the new chair of the organization.
Although Intel’s Shishpal Rawat, recently retired from Intel, is a hard act to follow as Accellera Chair given his long, productive years leading the organization, if anyone can do it Lu Dai can. He’s enthusiastic, energetic, optimistic, and an engineer – and not necessarily in that order.
Before talking about Accellera in our phone call this week, Dai spoke about DVCon, anchor tenant of Accellera’s outreach to design and verification engineers around the world. This next week, the Silicon Valley version will unfold in San Jose, with DVCon India happening in September, DVCon Europe in October, and the first-ever DVCon China in April.
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Tags: Accellera, DVCon, DVCon China, DVCon Europe, DVCon India, DVCon U.S., Lu Dai, Qualcomm, Shishpal Rawat
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Thursday, February 16th, 2017
Ted Miracco is CEO of SmartFlow Compliance Solutions, a company based in Los Angeles that provides automated tools to help software vendors combat piracy, copyright infringement, and under-compliance. At the company’s recent Anti-Piracy Summit, Miracco was impressed by four specific concerns of executives attending from the EDA and IP industries. The following blog, contributed by Miracco, describes those issues.
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The Four Hacking Issues Weighing on the Minds of EDA Executives
I like spending time with executives from the EDA industry, in part because I used to be an executive in that industry. Last fall at the SmartFlow Anti-Piracy Summit, I had conversations with a dozen or so executives and heard a new urgency in their voices for help solving the challenge of unauthorized use of software and semiconductor IP.
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Tags: David Locke Hall, SmartFlow Compliance Solutions, Ted Miracco
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Thursday, February 9th, 2017
Thanks to the staff of EDACafe, yet more video interviews are now available on the website. This content, recorded at last week’s DesignCon, continues to capture the technical expertise of those who pursue market excellence with today’s technology.
Those interviewed include: TE Connectivity’s Nathan Tracy, Rambus’ Mohit Gupta, Anritsu’s Joe Mallon, CST’s Klaus Krohne, Keysight Technologies’ Stephen Slater, DVT Solutions’ Brian Shumaker and Signal Microwave’s Bill Rosas, Mentor’s Dave Kohlmeier, ESD Alliance’s Bob Smith, Cadence’s Sam Chitwood, and Asteelflash’s Matheiu Kury.
You can see all of the DesignCon 2017 videos here.
Also of interest this year at DesignCon in Santa Clara, Steve Yamaguma was the winner of the Amazon Echo offered in a raffle in the EDACafe booth at the show.
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Tags: Bill Rosas, Bob Smith, Brian Shumaker, Dave Kohlmeier, DesignCon, Joe Mallon, Klaus Krohne, Matheiu Kury, Mohit Gupta, Nathan Tracy, Sam Chitwood, Sanjay Gangal, Stephen Slater, Steve Yamaguma
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Thursday, February 2nd, 2017
If you’re going to chair a conference, according to DVCon 2017 General Chair Dennis Brophy, don’t do any work. Instead just delegate, because if you’ve done that properly, the committees will craft a great program and a great gathering.
Hence, per Brophy, this year’s DVCon is going to be great. He’s done nothing, the committees have done everything, and their work has been inspired.
You must bring something to the effort, I insisted.
Brophy chuckled and deflected my question: “I’ll defer to Wally Rhines’ thesis: The learning curve definitely doesn’t stop, even though Moore’s Law is slowing. And there will be a lot of opportunity to learn this year at DVCon.
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Tags: Accellera, Dennis Brophy, DVCon 2017, IEEE 1800.2, SystemC, UVM
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Thursday, January 26th, 2017
If you were to attend only one Kaufman Award dinner throughout your career, tonight’s might have been the right choice: a lovely meal in downtown Silicon Valley, and presentations full of warmth, respect, humor and clear-eyed admissions, all in honor of CMU’s Dr. Andrzej Strojwas, long-time CTO at PDF Solutions.
Having interviewed Prof. Strojwas some months ago when he was first named the 2016 Kaufman Award winner, and knowing the event was in the capable hands of the ESD Alliance, this evening’s ambiance was not a complete surprise. But the display of emotion and palpable affection with which Dr. Strojwas is held by colleagues and family was almost mesmerizing.
In fact, as PDF CEO John Kibarian hit his stride at the podium, detailing the lifetime of achievements and leadership at the core of Dr. Strojwas’ award commendation, there could be no looking away.
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Tags: 2016 Phil Kaufman Award, Aart de Geus, Andrzej Strojwas, Carnegie Mellon, ESD Alliance, IEEE CEDA, John Kibarian, Lip-bu Tan, Lucio Lanza, PDF Solutions, Shishpal Rawat, Steve Director, Wojciech Maly
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Thursday, January 26th, 2017
Next week, DesignCon 2017 will be underway at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.
DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.
Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.
Also exhibiting this year at DesignCon will be our own EDACafe.
Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.
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Tags: Altium, Ansys, Applied Simulation, Cadence, DesignCon 2017, DipTrace, EDACafe.com, EMA, IBSystems, Mentor Graphics, Polar Instruments, Sanjay Gangal, SiSoft, SpeedIC, SPISim, Valydate, XJTAG
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Thursday, January 19th, 2017
Synopsys is undergoing a massive reset. Where not so long ago, it self-identified as the largest EDA company in the world, other words are now used to describe the enterprise: “Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.”
As compelling as that description may be, some observers are questioning whether the marked differences between maintaining expertise in chip design, verification, IP, and IP integration versus maintaining expertise in software integrity are too wide to make for easy co-habitation under one corporate roof.
Some would say putting EDA and chip design together with software security is not a good recipe for the long-term success of the company. But are these critics correct?
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Tags: Cigital, Codiscope, Coverity, Forcheck, SNPS, Synopsys
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