Posts Tagged ‘PSWG’
Wednesday, February 3rd, 2016
For more than four years now, Breker has branded itself as “The SoC Verification Company” and many people acknowledge our expertise in this domain. As we have discussed before on The Breker Trekker, our initial products focused on generating purely transactional tests for a simulation testbench, usually compliant with the Accellera Universal Verification Methodology (UVM) standard. When we extended our products to generate C code that runs on the embedded processors found within SoCs, we delivered on our “tagline” promise.
Since our early focus on simulating an SoC, we have expanded our technology and our product line to generate C test cases that run on embedded processors in emulation, FPGA prototypes, and actual silicon in the bring-up lab. In talking about what we do, we struggle to choose between “SoC” and “system” since for many of our customers the terms are synonymous. But we also have users verifying multi-SoC systems, and today we’d like to address that topic.
(more…)
Tags: application, Breker, bring-up lab, cache coherency, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
No Comments »
Wednesday, January 6th, 2016
It’s been more than a year since we presented the Breker view of system coverage in detail, so it’s time to revisit the topic. We first defined the notion of system coverage as measuring which realistic, system-level application scenarios have been exercised using the existing test cases. We then demonstrated how our graph-based scenario models are ideally suited to capture system coverage metrics and fine-tune them using graph constraints if needed.
More recently, we noted that the term “use cases” has become more widespread and introduced the example of a digital camera SoC to show the types of use cases that should be exercised. The measurement for this exercise is also system coverage, so the bottom line is that all these terms are really talking about the same thing. Using a regular expression, we might say:
[application|realistic] (scenario|use-case) coverage = system coverage
(more…)
Tags: Accellera, application, Breker, functional verification, graph, graph-based, node coverage, path coverage, PSWG, realistic use case, scenario model, simulation, SoC verification, system coverage, test case generator, Universal Verification Methodology, use-case coverage, uvm
No Comments »
Wednesday, December 30th, 2015
It’s becoming somewhat of a tradition here on The Breker Trekker blog to close each year with a list of gifts available from us to verification engineers. We started the series two years ago with an initial list focusing on our core benefits of automatic test case generation, system coverage, and reuse both vertically (IP to system) and horizontally (simulation to silicon). Last year’s post offered five more gifts reflecting additional products and new features added to our overall solution:
#5: Easier sequence specification in UVM testbenches.
#4: Faster coverage closure in UVM testbenches.
#3: Integration of system coverage with other coverage metrics.
#2: Debug of automatic test cases using standard tools.
#1: A fully automated solution for cache coherency verification.
Every one of the ten gifts from 2013 and 2014 is still available today for our customers. In addition, we have continued to evolve our Trek family of products and to deploy it on ever more challenging SoC verification projects. Without further ado, here is our all-new list of holiday gifts for the verification engineer in 2015:
(more…)
Tags: acceleration, Accellera, Breker, coherency, coverage, EDA, emulation, FPGA prototyping, functional verification, graph, level shifters, low power, platforms, power domains, PSWG, reuse, scenario model, silicon, simulation, SoC, SoC verification, system coverage, test generation, TrekApp, TrekSoC, TrekSoC-Si, TrekUVM, use cases, uvm, verification IP, VIP, virtual
No Comments »
Tuesday, December 22nd, 2015
In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.
This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.
(more…)
Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator
No Comments »
Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
(more…)
Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
No Comments »
Thursday, December 10th, 2015
The past two weeks, we’ve been having a bit of fun playing alchemist and letting readers in on some of the deep, dark secrets of graph-based verification technology. This week, we conclude the series by showing some additional capabilities for our scenario models that are easy to control and view in a graph visualization. Our point is, of course, that graphs are a natural way to represent data flow and verification intent with no advanced degrees from MIT, IIT, or Hogwarts required.
As a quick reminder, graph-based scenario models begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Breker’s Trek family can traverse the graph from left to right, randomizing selections to automatically generate test cases tailored to run in any target platform. Today, we continue using our example of a scenario model to verify that an automobile can move forward or stop.
(more…)
Tags: Accellera, Breker, constraints, cross-coverage, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, system-level coverage, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Thursday, December 3rd, 2015
Last week, we began exploring some of the ancient, mysterious powers of graph-based scenario models to show their power for verification and ability to capture the verification space, many aspects of the verification plan, and critical coverage metrics. We’re just kidding about the first part; there’s nothing at all mystical or magical about graphs. In fact, this series of posts is intended to show the opposite and demonstrate with a easy-to-follow example the value of graphs.
As we noted in our last post, graph-based scenario models are simple in concept: they begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. An automated tool such as Breker’s Trek family can traverse the graph from left to right, randomizing selections to generate test cases that can run in any target platform.
(more…)
Tags: Accellera, Breker, constraints, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Tuesday, November 24th, 2015
If there’s one thing that Breker is known for, it’s the use of graphs for verification. From our earliest days, we harnessed the abstraction and expressive power of graph-based scenario models to capture the verification space, many aspects of the verification plan, and critical coverage metrics. As we reported in a post a few weeks ago, it looks certain that the industry will follow our lead and base the upcoming standard from Accellera‘s Portable Stimulus Working Group (PSWG) on a graph representation.
As discussions have proceeded both within the PSWG and informally with interested parties, it has become clear that “graph” may not mean the same thing to all people. Our view of graphs is precisely defined in a way that makes it easy for users to create them and feasible for our tools to generated complex, multiprocessor test cases from them. Most of the key concepts can be communicated easily by the use of a familiar example, which we will begin in today’s post and continue next week.
(more…)
Tags: Accellera, Breker, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Tuesday, November 17th, 2015
In last week’s post, we dissected the results for verification languages and methodologies from a recent survey by Mentor Graphics and Wilson Research Group. The main result was that SystemVerilog is growing in popularity on all fronts, but we observed that C/C++ has a significant presence. We also argued that the survey’s focus on simulation likely resulted in C/C++ being under-represented since these languages are widely used for verification with hardware platforms and for silicon validation in the lab.
We see C/C++ as the common link for many types of programming activities, and so widely known that many consider it the lingua franca of software. Just type “lingua franca C/C++” into your favorite search engine and scan the results for some interesting arguments and a few counter-arguments. To be fair, some observers consider C the lingua franca and downplay C++. We tend to group them together since object-oriented programming is now widespread and so moving from C to C++ should be a natural transition.
(more…)
Tags: Accellera, API, Breker, C/C++, EDA, ESL, functional verification, horizontal reuse, Java, Mentor Graphics, PSWG, Python, Ruby, simulation, SoC verification, subsystem, SystemVerilog, uvm, vertical reuse, VHDL
No Comments »
Wednesday, November 11th, 2015
One of the cliches we hear from time to time in the industry is “designers want to stick with a single language, but verification engineers love learning new things.” The implication seems to be that because verification engineers have diverse jobs that require them to juggle lots of different tools and models, they necessarily have to learn new languages and methodologies on a regular basis. Of course, they may not actually love learning new languages; doing so may just be in the nature of their work.
Regardless of whether or not they “love” new languages, it is clear that most verification projects involve multiple languages and multiple approaches. One way to gauge the current situation is to turn to the excellent survey that Mentor Graphics performs with Wilson Research Group every couple of years. Harry Foster wrote a series of posts on the Mentor verification blog that give considerable insight into what verification (and design) engineers are doing on real projects.
(more…)
Tags: Accellera, API, Breker, C/C++, Cadence, e, EDA, ESL, functional verification, Harry Foster, horizontal reuse, Mentor Graphics, OVL, PSWG, simulation, SoC verification, subsystem, Synopsys, SystemC, SystemVerilog, Universal Verification Methodology, uvm, vertical reuse, VHDL
1 Comment »
|
