The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Top 5 Holiday Gifts for the Verification Engineer
December 30th, 2013 by Tom Anderson, VP of Marketing
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
#5: Relief from hand-writing verification test code. Our most advanced SoC customers hit the testbench wall several years ago, finding that the Universal Verification Methodology (UVM) doesn’t scale to the full-chip level and has no provision for code running on embedded processors. Many supplemented the UVM with hand-written embedded C tests. They found that it was very hard to develop tests to run in parallel and exercise concurrent data paths. Breker’s gift is the automatic generation of self-verifying, multi-threaded, multi-processor C test cases that run efficiently on the embedded processors in simulation and acceleration. TrekSoC is the product that provides this gift to you.
#4: Relief from hand-writing validation diagnostics. When the actual SoC arrives from the foundry, our customers want to bring it up in the lab with the goal of running full production code for hardware-software co-validation. However, booting an operating system rarely works immediately and it’s hard to debug any problems found in the process. Most validation teams hand-write diagnostics that check out each part of the SoC and look for any lingering hardware bugs before trying to run production software. Breker’s TrekSoC-Si product provides the gift of automatically generated self-verifying, multi-threaded, multi-processor C test cases that run on silicon in the lab. These same test cases run on other hardware platforms, including in-circuit emulation (ICE) and FPGA prototyping.
#3: Vertical verification IP reuse from block to system. One disadvantage of simulation testbenches is that a lot of rework is required to reuse verification IP (VIP) across multiple levels of the SoC project. In contrast, the graph-based scenario models used by TrekSoC and TrekSoC-Si to generate test cases are inherently scalable and reusable. The same model can be used to generate tests at the block level and then easily instantiated in higher-level models for a subsystem or a complete SoC.
#2: Horizontal verification IP reuse from electronic system level (ESL) to silicon. TrekSoC generates test cases for all simulation platforms, ranging from high-level ESL models through RTL simulation to simulation acceleration. TrekSoC-Si generates test cases for all hardware platforms, from ICE through FPGA prototypes to silicon. Both products use the same graph-based scenario models, which serve as truly reusable VIP throughout the entire SoC development process.
#1: Effortless system coverage reflecting end-use applications. Graph-based scenario models are unique is that they incorporate all three key aspects of verification: stimulus, expected response, and coverage. The gift to you is true system coverage extracted automatically from the scenario model. This coverage represents realistic application usage, for example, whether a smartphone SoC tries answering a call while composing a text message at the same that an application update is downloading.
Note that all five gifts are automatic benefits from your scenario models. For about the same effort as hand-writing one simulation test case or one validation diagnostic, you can develop a vertically and horizontally reusable scenario model capable of generating hundreds or thousands of test cases and providing a summary of system coverage. To take advantage of these gifts, please contact your local Breker sales representative and ask how to take an in-depth look at our products.
Thanks for your loyal readership, and Happy Holidays, everyone!
The truth is out there … sometimes it’s in a blog.
Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP