The Results Are In, and Graphs Win!

Anyone who has followed Breker for any length of time knows that our key technology is the ability to generate both Universal Verification Methodology (UVM) testbench transactions and C test cases running on SoC embedded processors automatically from graph-based scenario models. Yes, that’s a long sentence but it’s most of the “elevator pitch” that we might deliver to a potential investor or to a visitor at a trade show booth asking what we do.

For the purposes of today’s post, note that graphs are the root of the solution we provide. Ten years ago, when we first began talking about the idea of graphs as the basis for functional verification of complex chip designs, we were the proverbial pioneer with arrows in our back. But many successful customer engagements and the ever-rising need for better verification have validated our position. Graphs are clearly the “next big thing” in verification and we’d like to explain why.

Over the course of 125 posts on The Breker Trekker over the last two and a half years, the subject of graphs has cropped up many times. Some of the topics we’ve covered have included:

• Graphs are a natural and pleasant way to model verification intent
• Graphs define verification by beginning with the end in mind
• The result is that graphs are like pulling on a rope, not pushing it
• Graphs capture system-level coverage of realistic use cases
• Graphs enable vertical reuse from IP to cluster to system
• Graphs enable horizontal reuse across verification platforms
• Graphs enable intuitive forms of debug
• Pre-built graphs create apps, such as for cache coherency verification

Why do graphs have such interesting properties? In fact, there’s a significant body of research that suggests human brains organize knowledge in a graph-based structure. This may help explain why design and verification engineers find  creating a graph-based scenario model relatively natural. We were the pioneer in adopting graphs for verification, but we have to give credit to our friends at Mentor Graphics for also promoting this idea in recent years.

What’s changed just in the last few weeks, and the main reason for this post, is that the industry has lined up squarely behind graphs for verification. Several of our recent posts have discussed the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. This group is chartered to define a standard for portable tests, stimulus, and coverage that has many of the attributes listed above for graphs, most notably vertical and horizontal reuse from a single specification.

We’ve also talked about the press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the PSWG. Just in case anyone missed a key bullet in this press release, it was the following:

• The collaborative contribution includes … a model-based approach supporting graph-based descriptions of stimulus and test scenario

Let’s be honest: this is a big deal. All three EDA vendors with current products claiming to deliver some level of portable stimulus have agreed upon a graph-based input specification format. We’ve pledged not to reveal details of what’s going on within the PSWG, but we believe that it’s fair to say that all contributions under consideration are based on graphs. And so, on this basis, we claim that graphs have “won” by being selected as the enabler for portable stimulus.

Call us out for dancing in the end zone if you like, but we are deeply pleased to see our once-radical proposal to use graphs for verification become accepted in the industry. There is a lot yet to be resolved, including the standard syntax for specifying and controlling a graph. We will try to keep you posted, but we also urge you to join the PSWG if possible. We need as many experts as we can to define and guide the next big thing in verification.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP

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