Posts Tagged ‘PSWG’
Thursday, March 14th, 2019
The point of standards is to bring an industry together, to avoid duplication of effort, and to reduce risks associated with adoption of technology that may lock a user into a single vendor. These are some of the reasons why Breker was glad to see the creation of the Portable Stimulus working group within Accellera and actively participated in it since its inception. We donated technology and invested more time and effort, as a percentage of company size, than any other player. We were also glad to see the release of version 1.0 of the standard at DAC in 2018 – a huge step for the industry.
But was it enough? Some standards are ratified having been developed and refined by a single company and successfully proliferated across an industry, prior to donation to a standards body. Others are designed by committee and therefore run the risk of an unproven body of work captured as a hard to change standard. Sometimes this works well, other times, less so. It is only after the fact that you know if the committee got it right. So far the Portable Stimulus Standard is being tested by a relatively large number of companies with success, but there are still missing elements for a scalable solution. (more…)
Tags: Accellera, Breker, HSI, HSI Interface, Innovation Summit, PSWG, Verification 3.0
No Comments »
Thursday, August 23rd, 2018
With the release of the 1.0 version of the Portable Stimulus Standard (PSS), the industry now has a solid base on which to build solutions and to ensure that the time and investment made by users to create verification intent models is portable. This should allow them to assess tools and decide which one fits their requirements best and which ones will fulfill their roadmap into the future. Unfortunately, it is not quite as easy as that, because many users have already moved beyond the basics as represented in the standard. (more…)
Tags: Accellera, Breker, HSI, Lu Dai, PSS, PSWG, SystemVerilog
No Comments »
Thursday, September 8th, 2016
As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the verification flow and to be able to reuse it across designs. This will dramatically increase verification efficiency and establish verification methodologies that are likely to be used for the next couple of decades. (more…)
Tags: Accellera, Breker, EDA, functional verification, IBM, NVIDIA, portability, portable stimulus market leader, PSWG, reuse, SoC verification, software-driven verification, test generation, user advocate, verification efficiency, verification IP, verification methodology
No Comments »
Wednesday, August 24th, 2016
Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.
As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges
(more…)
Tags: acceleration, Accellera, Breker, Broadcom, Cadence, coverage, debug, dvcon, DVCon India, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, Infineon, Intel, mentor, multi-SoC, multi-threaded, multiprocessor, NXP, PSWG, Qualcomm, reuse, scenario model, simulation, SoC verification, software-driven verification, Synopsys, test generator, transactional, TVS, Universal Verification Methodology, UVC, uvm, VIP
No Comments »
Wednesday, August 10th, 2016
As some of you may have seen, two years ago the IEEE created an app that ranks the popularity of dozens of programming languages. They use twelve different metrics, from search results and social media mentions to technical publications and requirements listed in job openings. If you don’t like the way that they use these metrics, you can create your own ranking using your own mix. It’s really quite a clever idea and it generates lots of discussion every year.
For 2014 and 2015, C held the #2 spot, just below Java in the rankings. The big news this year is that C has edged into first place, although the top two spots remain very close as measured by the metrics the IEEE has chosen to use. C++ was in the #3 spot for the past two years, but for 2016 flipped places with Python. As you all know, we are strong advocates of C/C++ for verification and so we’d like to share some thoughts on these results and what they mean for our industry.
(more…)
Tags: acceleration, Accellera, API, Breker, C/C++, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, horizontal reuse, IEEE, Java, Mentor Graphics, multi-SoC, multiprocessor, Perl, programming languages, PSWG, Python, reuse, scenario model, simulation, SoC verification, software-driven verification, subsystem, SystemVerilog, test generator, testbench, Universal Verification Methodology, uvm, vertical reuse, VHDL
No Comments »
Wednesday, August 3rd, 2016
As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.
The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.
(more…)
Tags: acceleration, Accellera, Breker, coverage, debug, dvcon, DVCon India, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, Infineon, IP-XACT, multi-SoC, multi-threaded, multiprocessor, NXP, performance analysis, PSWG, reuse, scenario model, simulation, SoC verification, software-driven verification, test generator, transactional, Universal Verification Methodology, UPF3.0, UVC, uvm, VIP
No Comments »
Thursday, June 9th, 2016
We’ve just wrapped up the 53rd annual Design Automation Conference (DAC), held for just the second time in Austin. As we mentioned in our show preview last week, Breker was founded in Austin so it’s always nice to return to our roots. With its live music, countless good BBQ joints, and sense of history, Austin is always a fun place to visit. The city has a large high-tech workforce, so we expected crowds similar to those in San Francisco or San Diego.
To be honest, the exhibition floor looked rather quiet at times. With the wide aisles and many attendees clustered around the Big Three EDA vendors and those booths with entertainment or giveaways, other parts of the floor seemed forgotten. Fortunately, our booth was on the major cross aisle and we had the industry momentum around portable stimulus in our favor, so we had a very good show. We’ll discuss our results as we fill in a few highlights from the four days we were there.
(more…)
Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, cruise, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
No Comments »
Wednesday, June 1st, 2016
The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.
As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.
(more…)
Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
No Comments »
Wednesday, May 25th, 2016
Last week on The Breker Trekker, we talked about path constraints and how they differ from other kinds of constraints commonly used in SoC design and verification. Our whole approach to verification is based on graph-based scenario models, and constraints on the paths through the graph are a natural way to control how our Trek family of products automatically generates test cases. It’s easy to eliminate some paths, focus on others, or bias the randomization of selections. We believe that path constraints should be a part of any portable stimulus solution that meets the forthcoming Accellera standard.
We have heard some people in the industry argue that path constraints are not needed, and that value constraints would suffice. While we agree that value constraints are a familiar concept from the UVM and other constrained-random approaches, we do not feel that they are the best way to control the scenarios generated from a portable stimulus model. In today’s post we will expand on the example from last week and show how path constraints can handle a more complex design better than value constraints.
(more…)
Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
1 Comment »
Thursday, May 19th, 2016
As engineers, we take great pride in defining our terms carefully and using them precisely to try to avoid ambiguity or confusion. Many engineering specifications start with a glossary of terms and sometimes even a taxonomy showing how they are related. Sometimes though, natural language being inherently ambiguous, we find that we have overloaded the meaning of certain words in a way that can lead to precisely the confusion we seek to avoid.
One such word is “constraint” because it is used in several different contexts in chip design and verification. In today’s post we would like to discuss path constraints on a graph-based scenario model. We will explain how they differ from other forms of constraints and why path constraints are essential for any portable stimulus solution, including the Trek family of products from Breker.
(more…)
Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
2 Comments »
|
