Posts Tagged ‘System on Chip’
Monday, February 25th, 2013
So you thought our blog last week was our last prediction? Just kidding.
We actually have one more prophesy……from Michel Courtoy, esteemed EDA executive, entrepreneur and angel investor.
“As a member of the EDA community, when I look at 2013, I see a key dynamic in our customer base: chip = SoC. Across the board now, designs are created by combining multiple IPs from different sources that include embedded processors, multiple interfaces and memories. This is true across the spectrum from simple microcontrollers, to multi-function chips for consumer devices, all the way to the most complex multi-core microprocessors. Hence technologies that accelerate the design and verification of SoCs will thrive while technologies targeting the IP-level will find a saturated market.
Internal to the EDA market, we have been bombarded with messages of gloom triggered by the consolidation that has eliminated most ‘mid-size’ EDA suppliers, leaving mainly the ‘Big 3 and the 100 dwarfs’. Well, this might be the opportunity that the start-ups need: where will the Big 3 fill their shopping cart now when looking for new technologies? To stay competitive, the Big 3 have to go back to acquiring start-ups and find a way to monetize new technologies in their sales channel. This will reinvigorate the ecosystem for EDA start-ups and lead to more innovation.
(more…)
Tags: EDA, MIchel Courtoy, Semiconductor IP, SoC, System on Chip
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Wednesday, October 3rd, 2012
 Ashima Dabare  Saurabh Verma
On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.
Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!
Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?
Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.
One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.
Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.
Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.
I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.
The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.
Ed: So how would you sum up what CDC design needs in 2012?
Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!
Note: as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.
Note: Lee PR does work for Atrenta
Tags: Atrenta, CDC, CDC verification, Chip Design, Clock Domain, EDA, EDA DesignLine, EE Times, Electronic Design Automation, Network on Chip, NoC, semiconductors, SoC, System on Chip
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Tuesday, September 4th, 2012
 Jim Hogan  Ajoy Bose
Atrenta CEO Ajoy Bose and EDA visionary and investor Jim Hogan spoke at a recent National Institute of Technology (NIT) meeting on the momentous changes we see in who controls chip design these days. Clearly, systems companies like Apple define – even dictate – what they want from their silicon vendors..and these systems customers certainly want a lot more than they did ten years ago.
Jim tells us why we have to care:
Video Part 1
Video Part 2
Power Point Presentation
Ajoy shows us how to care:
Video Part 1
Video Part 2
Power Point Presentation
Lee PR does work for Atrenta
Tags: Ajoy Bose, Atrenta, Chip Design, EDA, Electronic Design Automation, Jim Hogan, National Institute of Technology, RTL, semiconductors, SoC, System Design, System on Chip
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Monday, August 20th, 2012
Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama. This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:
http://www.nikkeibp.co.jp/article/news/20120720/316569/
Lee PR does work for Atrenta
Tags: Atrenta, Chip Design, EDA, Electronic Design Automation, Nikkei, register transfer level, Renesas, RTL, Semiconductor IP, semiconductors, SoC, SpyGlass, SpyGlass Physical, System on Chip, Tech-On
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Monday, July 30th, 2012
 Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
Tags: acquisitions, Atrenta, EDA, Electronic Design Automation, Finance, functional verification, IP, IP qualification, IP reuse, NextOP, register transfer level, RTL, semiconductors, SoC, SoC Realization, System on Chip, verification
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Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
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Friday, May 25th, 2012
Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.
Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year. How? Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.
ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602. The company’s executives will be there to:
1) talk about its technology,
2) introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and
3) ensure that ICScape will be one of the EDA names that all of you will have heard of.
See what Paul McLellan, Mike Demler and Brian Bailey have to say about ICScape:
http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html
http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html
http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape
See you at DAC!
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Note: Lee PR does work for ICScape.
Tags: A/MS, analog/mixed-signal, Brian Bailey, DAC, Design Automation Conference, design closure, EDA, EE Daily News, EE Times, Electronics Design Automation, Finance, HES, Huada Empyrean, IC, ICScape, integrated circuits, Mike Demler, Paul McLellan, SemiWiki, SoC, SoC design, System on Chip
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Thursday, February 9th, 2012
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com
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Wednesday, February 1st, 2012
In 2012, we’ll see tablets and smartphones changing the world. That’s another way of saying Apple’s moves will have huge implications in semiconductors, foundries and EDA.
Apple’s use of the Samsung foundry has started an arms race between Samsung, TSMC and Global Foundries. Samsung is ramping up to meet the capabilities and capacity of TSMC. Intel is being pushed to stay ahead technologically and to consider new business models. Global Foundries continues to work to ramp its yields.
This situation will be good for semiconductor equipment and EDA vendors as well. Their tools will facilitate the new processes and the link between design and manufacturing.
Another element: in 2012, we’ll see the supply chain continue to consolidate. Why? The cost to design a complex SoC requires a big budget and a big market opportunity. Only the largest of semiconductor companies can tackle these designs. This increasing cost helps the FPGA vendors.
The foundries face increasing technology and capital requirements to move to new process nodes. Only a few will make it.
The public markets have been closed to EDA companies for a number of years making acquisition the most likely exit for EDA startups. Apache chose to be acquired by Ansys in 2011. It has been difficult for a new, large EDA competitor to emerge. This bodes well for Big EDA in its negotiations with Big Foundry and Big Semiconductor. In 2012 I believe there are several EDA companies poised to go public.
Who will be the beneficiary of these changes in 2012? Apple. Consumers should also benefit as new, leading edge fab capacity will be used to make exciting new devices.
John Barr
Portfolio Manager
Needham Aggressive Growth Fund
Needham Growth Fund
445 Park Avenue
New York, NY 10022
(212) 705-0462
Tags: 2012, Ansys, Apple, EDA, EDA & IP, Electronic Design Automation, Finance, foundries, Global Foundries, Intel, investment, IP, Lee PR, Needham, Samsung, Semiconductor IP, semiconductors, SoC, System on Chip, TSMC, www.leepr.com
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Wednesday, January 25th, 2012
On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power — I think we’ll see a move to optimize for power as a primary consideration.
On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.
On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics — a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes 🙂
Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com
Tags: 2012, ASIC, EDA, EDA & IP, EE Times, Electronic Design Automation, FPGA, Lee PR, low power, Maxfield High-Tech Consulting, Programmable Logic, Programmable Logic DesignLine, publishing, semiconductors, SoC, software, SRAM, System on Chip, textbooks, www.leepr.com
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