Posts Tagged ‘RTL’
Wednesday, August 8th, 2012
 We’ve heard from Jim Hogan and Gary Smith on recent acquisitions. Now industry analyst Mike Demler weighs in.
Ed: What does the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Mike: It probably goes without saying that these two acquisitions are very different, both in their objectives and impact on the industry. The bottom line on the NextOp acquisition is that it represents strategic maneuvering by Atrenta as they attempt to emerge from their 10-year gestation period, which is generally the limit for VC-funded startups. I provide a more detailed analysis in an Analysis Brief, which is available from the EE Daily News.
The Synopsys-Springsoft acquisition may finally fill the hole in analog/custom implementation that Synopsys has had. When the Laker tools came on the landscape, they immediately gave Cadence some competition for Virtuoso. Synopsys has never been able to accomplish that with Galaxy Custom Designer, nor its predecessor (Cosmos).
Ed: What sort of new day does it herald for EDA?
Mike: As far as meaning to the EDA industry overall, again there are two different answers. For Atrenta-NextOp, this serves as a bellwether for the entire group of ~10-year old EDA startups. What are their exit strategies?
For Synopsys-Springsoft, the answer is more complex, and goes beyond the immediate impact in the analog/custom design space. With ~$1B in acquisitions in less than a year, Synopsys is looking more and more like a huge EDA conglomerate. They are separating themselves further from the 2nd and 3rd place companies, at least in terms of size. The industry dynamics will inevitably change as a result.
Ed: What’s the significance?
Mike: In a nutshell – the EDA industry continues to shrink. Acquisitions mean lost jobs. With 10-years or more now the norm to grow an EDA company, other industries look more attractive, both for capital investment and for skilled engineers.
Lee PR does work for Atrenta
Tags: Atrenta, EDA, EE Daily News, Electronic Design Automation, Finance, investments, Mike Demler. Semiconductors, RTL, Semiconductor IP, Springsoft, Synopsys
No Comments »
Tuesday, August 7th, 2012
 Yesterday we heard from Jim Hogan on the NextOp acquisition. Today Gary Smith chimes in on NextOp and the recent Springsoft buyout.
Ed: What do the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Gary: Technology wise the Atrenta acquisition means that the Silicon Virtual Prototype is becoming a reality. Business wise it could be the start of the roll-up in the middle.
Springsoft was always a possible roller-upper but generally thought of as a long shot because of theirTaiwanheadquarters. Springsoft certainly makes Synopsys stronger, especially with the Laker analog product, but doesn’t affect the SVP or the RTL sign-off tool market. Debug is just being rolled up into the simulator.
Ed: What sort of new day does it herald for EDA?
Gary: With the creation of the SVP we now have the RTL sign-off established. This then is the breakpoint between design and implementation, just as the gate-level netlist was in the past. This will free up a large group of designers, and enable a new larger group of designers, which in-turn will cause the explosion of new systems development.
Ed: What’s the significance?
Gary: Growth, opportunity, money; the usual stuff.
Lee PR does work for Atrenta
Tags: acquisitions, Atrenta, buyouts, Chip Design, EDA, Electronics Design Automation, Finance, Gary Smith, NextOP, RTL, Semiconductor IP, semiconductors, Silicon Virtual Prototype, Springsoft, SVP, Synopsys
No Comments »
Monday, July 30th, 2012
 Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
Tags: acquisitions, Atrenta, EDA, Electronic Design Automation, Finance, functional verification, IP, IP qualification, IP reuse, NextOP, register transfer level, RTL, semiconductors, SoC, SoC Realization, System on Chip, verification
No Comments »
Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”
See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:
EDA Café Blog: What Would Joe Do?
EDA Express
EE Daily News
EE Times News & Analysis
EE Times: EDA DesignLine
Gabe on EDA
SemiWiki
System-Level Design
Tech Design Forums
————–
Lee PR does work for Atrenta
Tags: Assertion Synthesis, Atrenta, EDA, EDA Cafe, EDA DesignLine, EDA Tech Design Forums, EE Daily News, EE Times, Electronic Design Automation, Gabe on EDA, Gary Smith, Jim Hogan, M&A, NextOP, NextOp Software, register transfer level, RTL, Semiconductor IP, semiconductors, SemiWiki, software, System-Level Design, verification
No Comments »
Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
*******************************************************
© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
—————————-
Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
No Comments »
Friday, June 1st, 2012
Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA.
The talks will be held at Atrenta’s booth #2230.
Monday, June 4
9:30 am…..Jack Browne, Sonics
10:30 am…Frederic Rivoallon, Xilinx
2:00 pm…..Halim Theny, Vivante
Tuesday, June 5
10:30 am…Charlie Janac, Arteris
2:00 pm…..Frederic Rivoallon, Xilinx
3:00 pm…..Dan Nenni, SemiWiki
5:00 pm…..Jack Browne, Sonics
Wednesday, June 6
10:30 am…Charlie Janac, Arteris
12:30 pm…Jim Hogan
……………………….
Note: Lee PR does work for Atrenta
Tags: 49DAC, Arteris, Atrenta, DAC, Design Automation Conference, EDA, Electronic Design Automation, investments, Jim Hogan, RTL, Sonics, SpyGlass, Vivante, Xilinx
No Comments »
Thursday, May 31st, 2012
 I recently talked with Atrenta’s senior director of product marketing, Kiran Vittal, about power management/optimization trends and approaches that we’ll see at DAC next week.
Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year?
Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power.
It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time.
Ed: So what approaches are we going to hear about @ DAC?
Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off.
Ed: How do they stack up?
Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips.
Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him!
……………..
Note: Lee PR does work for Atrenta
Tags: 49DAC, Atrenta, DAC 2012, Kiran Vittal, power management, power optimization, RTL
No Comments »
Tuesday, May 15th, 2012
Maybe Atrenta is saying goodbye to the thought-bubble guy…..
Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.
Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products. Sort of the mother ship that all Atrenta products are based on.
So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.
(more…)
Tags: 3D IC, Atrenta, Chip Design, DAC, DAC 2012, Design Automation Conference, EDA, Electronic Design Automation, GUI, IP quality, RTL, SpyGlass
No Comments »
Monday, January 18th, 2010
2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.
Here’s what they said.
Karen Bartleson, Blogger, The Standards Game, Synopsys
http://synopsysoc.org/thestandardsgame/
The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.
Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.
LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people – who today are curious or skeptical – as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.
The EDA world won’t change overnight, but the trends in social media will be noticeable.
Graham Bell, Director of Sales and Marketing, EDACafe
http://www10.edacafe.com/blogs/grahambell/
The BIG trend will be that designers need ALL of the technology that EDA companies have been working on and introduced in the last 18 months.
There is a lot of design work being done at 45nm and all the established tools are running at the edge of their capabilities.
New generations of parasitic extraction, static and statistical timing analysis, and automated property verification are just some of the important technologies that will be needed by design teams.
Mike Gianfagna, Vice President, Marketing, Atrenta, Inc.
http://www.atrenta.com
In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.
Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.
Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.
This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.
Richard Goering, longtime EDA editor and currently manager of the Cadence Industry Insights blog
http://www.cadence.com/Community/blogs/ii
I think the Big EDA Trend for 2010 will be SoC integration.
There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.
ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.
Harry Gries, the ASIC Guy, EDA blogger
http://theasicguy.com/
As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.
A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.
I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.
Grant Martin, EDA blogger
http://www.chipdesignmag.com/martins/
In 2010, we’ll see the steady progress towards usable ESL tool and methodology adoption by design groups.
The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.
(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )
Dan Nenni, EDA blogger
http://danielnenni.com/
For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.
The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles – they will continue to suffer the slings and arrows of outrageous economic misfortune.
Coby Zelnik, CEO, Sagantec North America, Inc.
http://www.sagantec.com
In 2010, we will see more designs taping out in 40nm.
In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.
– end –
Tags: 3D, architectural, Coby Zelnik, Dan Nenni, EDA trends, ESL, Graham Bell, Grant Martin, Harry the ASIC Guy, high level synthesis, IP-XACT, Karen Bartleson, Mike Gianfaga, power, Richard Goering, RTL, social media, verification
1 Comment »
|
We’ve heard from Jim Hogan and Gary Smith on recent acquisitions. Now industry analyst Mike Demler weighs in.
