The Dominion of Design

Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC

 
May 5th, 2014 by Sanjay Gangal

What would the Design Automation Conference (DAC) be without a verification panel or two? This year, one in particular takes a look at a variety of verification technologies. Titled, “The Asymptote of Verification,” it will be moderated by Bryon Moyer of EE Journal and held Monday, June 2, from 5:15 p.m. until 6 p.m. in the Pavilion (Booth #313) on the exhibit floor.

Proposed and organized by Graham Bell of Real Intent, users make up the panel and include Brian Hunter of Cavium, Holger Busch at Infineon Technologies and Bill Steinmetz from NVIDIA. Special thanks go to Breker, OneSpin and Real Intent for securing these three experts who will share their real-world experiences with formal verification, static RTL analysis, and graph-based verification. Oh yes, they are users of Breker, OneSpin and Real Intent tools.

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The Dell Precision M2800 Mobile Workstation is Available to Help Inspire Innovation for Design Professionals and Students

 
May 1st, 2014 by Andy Rhodes

The evolution of digital content creation has unleashed the productivity of engineers, designers, creative professionals and students everywhere, but it has also set corresponding expectations incredibly high for that productivity as well, making it crucial for those individuals to use the proper tools to help their visions to come to life. Professional and aspiring engineers and designers cannot do their job these days without specialized applications for 3D modeling, digital content creation, and computer aided engineering and design such as Adobe Creative Cloud and AutoCAD. The problem is, for some, they’re being forced to run these applications on notebooks or desktops that don’t have enough power to generate the performance they need because they can’t afford a traditional workstation.

Dell Precision M2800

Dell Precision M2800

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Intel Engineer Reimagines Earbuds for Smartphones

 
April 18th, 2014 by Sanjay Gangal

 Article source: Intel Free Press

Engineer Indira Negi worked on the design of Intel smart earbuds

Indira Negi brings passion for running, biometric experience and maker skills to development of Intel smart earbuds.

When she literally jogged on-stage to join Intel CEO Brian Krzanich in his opening keynote at International CES in Las Vegas, engineer Indira Negi was there to demonstrate the Intel smart earbuds that she and her team had developed, but the “smart” design she showed off also helped solve an issue the avid runner had personally encountered.

Indira Negi at CES with Intel CEO Brian Krzanich demo Intel smart earbuds

“I am a runner — I get hives from the sun, I have to run with gloves on,” said Negi about running with a smartphone. “That means when there is a bad song, I have to take out my phone, take off my gloves, unlock my phone and change the song.”

Starting from solving a problem that she knew all too well, Negi, a sensors systems engineer in the Intel New Devices Group, and a team set out to create a device and software that would monitor heart rate and adjust music playback based on sensor feedback. The result was the Intel smart earbuds reference design, developed in collaboration with Valencell.

Negi’s study of bioelectronics and biosensors in graduate school — she earned a master’s degree in electrical engineering from Arizona State — lent her a keen appreciation of the value of biometric monitoring.

One project she worked on while at ASU measured stress levels in saliva using specially treated paper. When you are working out, you are stressing your body in a positive way, explained Negi. If you work out too hard, this becomes negative stress, which can increase the chances of getting injured. She also worked on molecular imprinted polymers while at ASU coated with biochemical sensors that reacted only to specific molecules.

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Will Verification Allow Time for Design?

 
December 2nd, 2013 by Sanjay Gangal

Article source: TVS

Design engineers are increasingly spending their time on verification. Research suggests that it is now more than 50% of their time and, according to Harry Foster of Mentor Graphics in his lighter moments, if we continue the current linear trend then it will reach 100% by 2030! So why is verification so demanding? It seems that IP reuse has enabled designers to create larger, more complex designs to keep pace with our manufacturing capability but our verification productivity has not kept pace.

Looking to tools for productivity gains, EDAC (the EDA Consortium) reported that the overall EDA verification market grew by 38% from 2010 to 2012 with emulation up by 94%. But, as Mark Olen of Mentor pointed out “if Henry Ford had asked people what they wanted, they would have said faster horses”. So innovation is also required and Chris Brown of Broadcom set EDA companies the challenge of “collaborative competition” through standards. For example, UCIS has enabled TVS to build an innovative requirements sign off tool (asureSign) by reading verification data from multiple tools.

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Topological insulators: Breaking symmetry for faster computers

 
November 25th, 2013 by Sanjay Gangal

Article Source: Tokyo Institute of Technology, Center for Public Information

A new compound developed at Tokyo Tech shows highly unusual conducting properties that could be used in future electronic components. The details are described in the November 2013 issue of Tokyo Institute of Technology Bulletin:

http://www.titech.ac.jp/english/news/2013/024244.html

Ordinary insulating solids, such as diamond, have energy bands that are fully occupied by electrons. The conducting band is so far away from the valence band in diamond that electrons do not have sufficient energy to move – the ‘band gap’ is large – therefore no electric current can be carried.

In recent years, researchers have become interested in materials called topological insulators (TIs), which act as insulators on the inside, but are highly conductive on their surfaces. In TIs, an exceptionally strong spin-orbit interaction inverts the energy gap between occupied and empty states, so that electrons at the surface can flow across the gap. These properties are intrinsic to the material, meaning a TI remains conductive even if its surface is not perfect.

Now, an international team of scientists from Japan, the UK and the USA, led by Takao Sasagawa at Tokyo Institute of Technology, have successfully developed a new TI from bismuth, tellurium and chlorine (BiTeCl). Their new TI is inversion asymmetric, meaning it has different electronic states, and therefore different polarities, on each crystal surface. As a result, it exhibits many topological effects that have not been seen experimentally before.

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Unravelling the mind-body connection with power-efficient IC chip jointly developed by A*STAR IME, NTU and NUS

 
November 25th, 2013 by Sanjay Gangal

Article source: IME

Despite the advances in neuroscience research, the human brain remains a complex puzzle with questions unanswered on how it controls human behaviour, cognitive functions and movements.  Scientists from A*STAR Institute of Microelectronics (IME), Nanyang Technological University (NTU) and National University of Singapore (NUS) have jointly developed and demonstrated an integrated circuit (IC) chip with record-low power consumption for direct recording of brain activities. This breakthrough minimises the patient’s exposure to electromagnetic radiation and heat during the recording process, making it possible to integrate greater number of channels (>100 channels) to acquire more comprehensive profile of brain signals, paving the way to unlock the mystery behind the complex mind-body connection.

Neural recording system is a vital tool to acquire and process brain signals, and is also applied in artificial limb control (or neural prosthesis) treatments for paralyzed patients. The system comprises multiple electrodes for data acquisition and is implanted within the skull during the operation. The implantability of the system places tight limits on its size and power consumption, while at the same time demanding sufficient performance to record good quality data.

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Using Simulation to Optimize Safety, Performance, and Cost Savings When Integrating an Antenna Onto a Platform

 
February 7th, 2013 by Sanjay Gangal

Article source: Remcom

Successful integration of an antenna onto a vehicle platform poses many challenges.  Vehicle features impact antenna performance by blocking, reflecting or reradiating energy, and co-site interference can impair the effectiveness of multi-antenna configurations.  Platform motion and environmental factors such as terrain and buildings may reduce system effectiveness in actual op
erational conditions.  Furthermore, radiation hazards may pose risks to nearby personnel.  Modeling and simulation provides a powerful tool to aid in understanding these issues and developing solutions.  This article provides a variety of examples of simulation-based assessments used to analyze antenna performance, identify problems, and evaluate potential solutions.

The key benefit of simulation-based assessment is that it is relatively fast and cost-effective compared to physical system modification and measurement.  The lead times and costs associated with scheduling measurements in an anechoic chamber or at an outdoor test facility sometimes strain schedules and budgets.  Modeling and simulation can assess options and tradeoffs in order to select a small number of planned approaches well before any physical testing occurs; as a result, experimental design focuses on verifying planned approaches and fine-tuning alternatives demonstrated to be effective in simulations.  This approach reduces the risk of encountering problems that require retesting, costly redesign or introduce dangerous in-theater behavior.

In addition, a number of challenges arise when attempting to perform exhaustive laboratory or field testing on an integrated system.  Some potential issues include:

  • Available measurement facilities may not be able to accommodate larger platforms
  • Facilities may not be able to handle the full range of frequencies for the system(s) under test
  • Comprehensive in situ measurements may be difficult or impractical for operational conditions (e.g., aircraft in flight or a HMMWV in an urban environment)
  • In-theater modifications could require additional testing

A comprehensive modeling and simulation toolset allows an organization to overcome these challenges by being able to simulate any number of conditions, identify and resolve key issues, and reserve the use of physical measurements to confirm successful pre-test, simulation-based assessments.  The remainder of this article provides several examples demonstrating typical simulation-based assessments to identify and resolve issues related to antenna performance and integration onto vehicles.

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MIT researchers improve quantum-dot performance

 
February 4th, 2013 by Sanjay Gangal

Written by: David L. Chandler, MIT News Office

New production method could enable everything from more efficient computer displays to enhanced biomedical testing.

CAMBRIDGE, Mass. — Quantum dots — tiny particles that emit light in a dazzling array of glowing colors — have the potential for many applications, but have faced a series of hurdles to improved performance. But an MIT team says that it has succeeded in overcoming all these obstacles at once, while earlier efforts have only been able to tackle them one or a few at a time.

Moungi G. Bawendi

Quantum dots — in this case, a specific type called colloidal quantum dots — are tiny particles of semiconductor material that are so small that their properties differ from those of the bulk material: They are governed in part by the laws of quantum mechanics that describe how atoms and subatomic particles behave. When illuminated with ultraviolet light, the dots fluoresce brightly in a range of colors, determined by the sizes of the particles.

First discovered in the 1980s, these materials have been the focus of intense research because of their potential to provide significant advantages in a wide variety of optical applications, but their actual usage has been limited by several factors. Now, research published this week in the journal Nature Materials by MIT chemistry postdoc Ou Chen, Moungi Bawendi, the Lester Wolfe Professor of Chemistry, and several others raises the prospect that these limiting factors can all be overcome.

The new process developed by the MIT team produces quantum dots with four important qualities: uniform sizes and shapes; bright emissions, producing close to 100 percent emission efficiency; a very narrow peak of emissions, meaning that the colors emitted by the particles can be precisely controlled; and an elimination of a tendency to blink on and off, which limited the usefulness of earlier quantum-dot applications.

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Cadence, ARM and Samsung Tapeout Industry’s First Cortex-A-Based 14nm/FinFET Chip

 
December 20th, 2012 by Sanjay Gangal

ARM (LSE: ARM) (NASDAQ: ARMH) and Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the tape-out of the first 14-nanometer test chip implementation of the high-performance ARM® Cortex™-A7 processor, the most energy-efficient applications processor from ARM. Designed with a complete Cadence® RTL-to-signoff flow, the chip is the first to target Samsung’s 14-nanometer FinFET process, accelerating the continuing move to high-density, high-performance and ultra-low power SoCs for future smartphones, tablets and all other advanced mobile devices.

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“Kilopass Roadmap for Advanced TSMC Processes” by Harry Luan, CTO at Kilopass Technology

 
November 5th, 2012 by Sanjay Gangal

Article source: Kilopass Technology

“Kilopass Roadmap for Advanced TSMC Processes” by Harry Luan, chief technology officer at Kilopass Technology Inc., was presented at the 2012 TSMC Open Innovation Platform Ecosystem Conference on Tuesday, October 16, at 4:30 p.m. in the San Jose Convention Center, San Jose, California. Kilopass is a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP).

Kilopass



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