Posts Tagged ‘EDA’
Monday, February 17th, 2014
Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.
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Tags: 3D ICs, Cadence, Chip Design, EDA, EDA & IP, Electronic Design Automation, FinFETs, foundries, foundry, Intellectual property, Lee Public Relations, Mike Demler, Moore's Law, Semiconductor IP, semiconductors, SoC, Synopsys, System on Chip, The Linley Group, wearables, www.leepr.com
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Wednesday, February 12th, 2014
Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014.
“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.
At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”
Tags: Bryon Moyer, Chip Design, EDA, EDA & IP, EE Journal, Electronic Design Automation, FinFETs, Intellectual property, IP, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com
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Sunday, February 9th, 2014
Next up is Brian Bailey, Technology Editor/EDA, for Semiconductor Engineering, who has shared his forecast for EDA in 2014.
“Over the next couple of years there will be an increase in ASIC starts, but not all of these will be for the latest technology nodes or be the massive chips we have come to expect. The new starts will be smaller chips that form the leaves of the Internet of Things, things such as sensors with small amounts of processing and communications. They will be targeting older processes, such as 90nm. Margins on these devices will be slim but volumes high. I see the designers of these products requiring a different mix of capabilities in their EDA tools and different price points. It may create an interesting opportunity for the second tier EDA companies to become significantly bigger.”
Tags: Brian Bailey, Chip Design, EDA, Electronic Design Automation, Lee PR, Semiconductor Engineering, semiconductors, SoC, System on Chip, www.leepr.com
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Thursday, February 6th, 2014
 Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014.
“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense. Here is why.
‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs. Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.
The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. (more…)
Tags: Chip Design, EDA, EDA & IP, Electronic Design Automation, Intellectual property, IP, Lee PR, Lee Public Relations, Saankhya Labs, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com
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Monday, February 3rd, 2014
 Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
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Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Lee Public Relations, RTL, Semiconductor IP, SoC, System on Chip, www.leepr.com
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Wednesday, January 29th, 2014
 Next up in our series is Simon Bloch’s forecast for 2014. Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.
“The future of electronics is looking bright! Market forecasters predict growth in literally every category of electronic markets ranging from smart mobile and wearable devices, appliances and sensors connected to a network of Internet of Everything to smart connected cars and cities.
In today’s electronics products, sophisticated hardware is becoming insufficient for product success. Many layers of stacked software control the underlying hardware and determine a product’s competitiveness via functionality, performance, power and cost. And while there is always going to be a need to create new semiconductor components and IC companies will need EDA tools, EDA vendors need to expand the view of Electronics and treat software stack as an integrated part of EDA.
There are many opportunities to come up with products in the software stack space around Linux/Android operating systems and in the area of hardware virtualization. Just last month, CyanogenMod, a company that provides Android based software widely used in the mobile industry, secured $23 million in funding from top tier VCs. CyanogenMod is a software stack product and contains many features not found in Google versions of the operating system.
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Tags: Chip Design, CyanogenMod, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, Internet of Things, IoT, IP, Lee PR, Lee Public Relations, Samsung, SDA, Semiconductor IP, semiconductors, SoC, Software Design Automation, System on Chip, www.leepr.com
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Monday, January 27th, 2014
 We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Tags: 2014, Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, IP integration, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, SoC, System on Chip
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Sunday, January 19th, 2014
Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….
“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models. Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.
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Tags: EDA, EDA & IP, Electronic Design Automation, Finance, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, SK telecom Americas, SKTA Innopartners, SoC, VC, Venture Capital
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Tuesday, January 14th, 2014
 Back in December, Liz and I figured that it’d be a good time to ask chip and EDA/IP industry folks:
1) what will chip companies need from their EDA/IP vendors in 2014
and
2) what will we see develop in EDA/IP in 2014?
We thought that Jim Hogan could probably respond to both questions. He did us one better…he provided the context for us to ask these questions. While he has advice for the chip and EDA/IP vendors, what’s compelling is what Jim sees as driving design trends.
What does Jim see coming up, starting in 2014? First off, for a variety of economic reasons, he sees a lot more money becoming available for R&D. What are some of those economic dynamics? The US will become a larger oil producer than Saudi Arabia by 2020 (or maybe as early as 2015) and entirely oil-self-sufficient by 2020. Oil will become a lot cheaper as a result and the US will swing a current $1.5T deficit into a $500B one.*
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Tags: EDA, IoT, Jim Hogan, Lee PR, semiconductors, trends for 2014, wearable devices
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Wednesday, October 23rd, 2013
My colleague Liz Massingill spoke with IPextreme CEO Warren Savage about her approach to PR, i.e., what she wants to accomplish on behalf of her clients.
The main message? It’s all about the story…the company’s story…and how Liz creates it, substantiates it, reinforces it. In the end, it’s all about putting a human face on the faceless company to give it personality, an image, a life. An entity that customers want to do business with.
Check out the video:
Tags: creating the PR story for clients, EDA, high tech PR, IP, Lee PR, Liz Massingill, semiconductors, Warren Savage
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