Archive for the ‘Uncategorized’ Category
Wednesday, October 3rd, 2012
 Ashima Dabare  Saurabh Verma
On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.
Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!
Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?
Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.
One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.
Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.
Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.
I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.
The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.
Ed: So how would you sum up what CDC design needs in 2012?
Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!
Note: as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.
Note: Lee PR does work for Atrenta
Tags: Atrenta, CDC, CDC verification, Chip Design, Clock Domain, EDA, EDA DesignLine, EE Times, Electronic Design Automation, Network on Chip, NoC, semiconductors, SoC, System on Chip
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Monday, September 10th, 2012
 Piyush Sancheti
Why can 3rd party IP impede a design getting to tapeout? Why is IP reuse costing design projects more time and effort? And what can we do about it? Piyush Sancheti, VP of Product Marketing at Atrenta, explores these issues and answers some of these questions in the viewpoint below on the GSA IP Working Group blog:
http://www.gsaglobal.org/2012/08/general-working-group-activity-recruiting-meeting-locations-updates-agendas/
Lee PR does work for Atrenta
Tags: Atrenta, Chip Design, EDA, Electronic Design Automation, IP, Piyush Sancheti, Semiconductor IP
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Tuesday, September 4th, 2012
 Jim Hogan  Ajoy Bose
Atrenta CEO Ajoy Bose and EDA visionary and investor Jim Hogan spoke at a recent National Institute of Technology (NIT) meeting on the momentous changes we see in who controls chip design these days. Clearly, systems companies like Apple define – even dictate – what they want from their silicon vendors..and these systems customers certainly want a lot more than they did ten years ago.
Jim tells us why we have to care:
Video Part 1
Video Part 2
Power Point Presentation
Ajoy shows us how to care:
Video Part 1
Video Part 2
Power Point Presentation
Lee PR does work for Atrenta
Tags: Ajoy Bose, Atrenta, Chip Design, EDA, Electronic Design Automation, Jim Hogan, National Institute of Technology, RTL, semiconductors, SoC, System Design, System on Chip
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Monday, August 20th, 2012
Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama. This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:
http://www.nikkeibp.co.jp/article/news/20120720/316569/
Lee PR does work for Atrenta
Tags: Atrenta, Chip Design, EDA, Electronic Design Automation, Nikkei, register transfer level, Renesas, RTL, Semiconductor IP, semiconductors, SoC, SpyGlass, SpyGlass Physical, System on Chip, Tech-On
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Wednesday, August 8th, 2012
 We’ve heard from Jim Hogan and Gary Smith on recent acquisitions. Now industry analyst Mike Demler weighs in.
Ed: What does the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Mike: It probably goes without saying that these two acquisitions are very different, both in their objectives and impact on the industry. The bottom line on the NextOp acquisition is that it represents strategic maneuvering by Atrenta as they attempt to emerge from their 10-year gestation period, which is generally the limit for VC-funded startups. I provide a more detailed analysis in an Analysis Brief, which is available from the EE Daily News.
The Synopsys-Springsoft acquisition may finally fill the hole in analog/custom implementation that Synopsys has had. When the Laker tools came on the landscape, they immediately gave Cadence some competition for Virtuoso. Synopsys has never been able to accomplish that with Galaxy Custom Designer, nor its predecessor (Cosmos).
Ed: What sort of new day does it herald for EDA?
Mike: As far as meaning to the EDA industry overall, again there are two different answers. For Atrenta-NextOp, this serves as a bellwether for the entire group of ~10-year old EDA startups. What are their exit strategies?
For Synopsys-Springsoft, the answer is more complex, and goes beyond the immediate impact in the analog/custom design space. With ~$1B in acquisitions in less than a year, Synopsys is looking more and more like a huge EDA conglomerate. They are separating themselves further from the 2nd and 3rd place companies, at least in terms of size. The industry dynamics will inevitably change as a result.
Ed: What’s the significance?
Mike: In a nutshell – the EDA industry continues to shrink. Acquisitions mean lost jobs. With 10-years or more now the norm to grow an EDA company, other industries look more attractive, both for capital investment and for skilled engineers.
Lee PR does work for Atrenta
Tags: Atrenta, EDA, EE Daily News, Electronic Design Automation, Finance, investments, Mike Demler. Semiconductors, RTL, Semiconductor IP, Springsoft, Synopsys
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Tuesday, August 7th, 2012
 Yesterday we heard from Jim Hogan on the NextOp acquisition. Today Gary Smith chimes in on NextOp and the recent Springsoft buyout.
Ed: What do the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Gary: Technology wise the Atrenta acquisition means that the Silicon Virtual Prototype is becoming a reality. Business wise it could be the start of the roll-up in the middle.
Springsoft was always a possible roller-upper but generally thought of as a long shot because of theirTaiwanheadquarters. Springsoft certainly makes Synopsys stronger, especially with the Laker analog product, but doesn’t affect the SVP or the RTL sign-off tool market. Debug is just being rolled up into the simulator.
Ed: What sort of new day does it herald for EDA?
Gary: With the creation of the SVP we now have the RTL sign-off established. This then is the breakpoint between design and implementation, just as the gate-level netlist was in the past. This will free up a large group of designers, and enable a new larger group of designers, which in-turn will cause the explosion of new systems development.
Ed: What’s the significance?
Gary: Growth, opportunity, money; the usual stuff.
Lee PR does work for Atrenta
Tags: acquisitions, Atrenta, buyouts, Chip Design, EDA, Electronics Design Automation, Finance, Gary Smith, NextOP, RTL, Semiconductor IP, semiconductors, Silicon Virtual Prototype, Springsoft, SVP, Synopsys
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Monday, August 6th, 2012
We’ve seen several acquisitions in the past month or so…and wanted to get a sense of what these purchases might or might not indicate about where EDA is going. So we went to the premier visionary and investor to get his take on how the EDA world will be affected by this apparent consolidation.
Ed: What do these acquisitions over the past month or so mean to EDA?
Jim: I like the Atrenta NextOp acquisition for several of points of view. In my world mergers are successful in EDA if:
1. there is no product overlap
2. the sales channel can immediately sell the product. Usually this means that the AEs support it or at least will be product within 30 days of purchase.
There is a ton of synergy with the Atrenta sales channel. This is important to ensure the ROI is met, typically a two to three year process.
3. customers support the merger. In other words, they see that the product is going to be continued to be supported with R&D and AEs.
4. the team remains at least two years to ensure intellectual property transition. In the case of Atrenta and NextOp, I believe all conditions are being met. Thus I expect a successful integration of NextOp and ROI.
In addition it speaks to Atrenta’s forward progress to being an IPO candidate. One issue for EDA is that companies exiting over the last ten years have been through acquisition. If we can see an IPO of a well-run and well-performing company, it attracts the attention of shareholders but also ensures an exit other than acquisition for other EDA companies. This will attract investors and thus we’ll see startups funded. This is a win-win for the entire ecosphere including customers.
I believe one of the key ingredients in an EDA company going public besides top line revenue of greater than $50m with 25% CAGR and margin of $10m or greater is the ability of the management team to acquire and integrate complementary startups. With Atrenta acquiring NextOp, I believe they are on their way.
Good luck to them because their IPO will be good for EDA by bringing excitement and notice to the sector.
Lee PR does work for Atrenta
Tags: Atrenta, EDA, Electronic Design Automation, Finance, functional verification, Jim Hogan, mergers, NextOP, Semiconductor IP, semiconductors
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Monday, July 30th, 2012
 Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
Tags: acquisitions, Atrenta, EDA, Electronic Design Automation, Finance, functional verification, IP, IP qualification, IP reuse, NextOP, register transfer level, RTL, semiconductors, SoC, SoC Realization, System on Chip, verification
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Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”
See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:
EDA Café Blog: What Would Joe Do?
EDA Express
EE Daily News
EE Times News & Analysis
EE Times: EDA DesignLine
Gabe on EDA
SemiWiki
System-Level Design
Tech Design Forums
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Lee PR does work for Atrenta
Tags: Assertion Synthesis, Atrenta, EDA, EDA Cafe, EDA DesignLine, EDA Tech Design Forums, EE Daily News, EE Times, Electronic Design Automation, Gabe on EDA, Gary Smith, Jim Hogan, M&A, NextOP, NextOp Software, register transfer level, RTL, Semiconductor IP, semiconductors, SemiWiki, software, System-Level Design, verification
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Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
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