Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we’ll dive much deeper into the transaction-level co-emulation methodology.
Aldec Design and Verification
Posts Tagged ‘SoC’
SCE-MI for SoC Verification
Wednesday, September 18th, 2013The WHAT is mandatory but the HOW is entirely optional
Monday, September 9th, 2013
You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.
Let’s break down just one part of the “How” or implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
The Magic of CyberWorkBench
Thursday, August 22nd, 2013
Dr. Benjamin Carrion Schafer, Assistant Professor at Hong Kong Polytechnic University (and longtime fan of Aldec’s latest offering, CyberworkBench from NEC) was kind enough to author a guest blog for Aldec. Here’s an excerpt:
My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth – was that they had hired a magician.
This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.
As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.
For the rest of this article, visit the Aldec Design and Verification Blog.
Aldec and Xilinx, Partnered for Success
Monday, July 8th, 2013HW/SW Emulation and Functional Verification of Xilinx FPGAs
As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend “Smarter 2013”, Xilinx’ annual Technical Sales Conference.
Since Aldec is a Xilinx Alliance Member, we have been invited to showcase our solutions at their conference’s Partner Night. Working closely with key technology partnerships like Xilinx has long been the cornerstone to Aldec’s success. Our mutual customers have benefited from these alliances, the result of hard work, open communication and close interaction between our teams.
Most recently, we’ve been syncing with our counterparts at Xilinx to fulfill the verification requirements of the newest SoC designs, as Aldec provides EDA solutions at every stage of development. Users can leverage the latest Xilinx ISE and Vivado design suites to simulate and verify designs in Aldec Active-HDL and Riviera-PRO, or incorporate Aldec FPGA-based prototyping boards utilizing Virtex-7 FPGAs for hardware emulation and SoC prototyping.
DO-254: Insights from a DER
Wednesday, June 26th, 2013
An Interview with FAA Consultant DER, Randall Fulton
A few weeks ago I had the opportunity to sit down with an avionics industry certification expert, FAA Consultant Designated Engineering Representative (DER), Randall Fulton. We began discussing common mistakes in DO-254 projects, and then branched out to many different areas including future of DO-254, industry engineering best practices, and his advice to organizations new to DO-254.
Louie: In your experience, what are the common mistakes in DO-254 projects?
Randall: Starting certification liaison activities and the SOI-1 planning audit after the design already exists. Many projects also need to read the additional guidance from the FAA in Order 8110.105 to understand the impact and be prepared to show the data to satisfy the Order. Organizations also underestimate the resources required for a project. This includes staffing as well as managing all the data. Another common area is not appreciating the impact of effective requirements writing skills.
Back from DAC
Tuesday, June 11th, 2013Functional Verification Insights from Austin
I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.
Conference itself
One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.
Register for Aldec Technical Sessions & Demos at DAC 2013
Thursday, May 16th, 2013
This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.
We invite you to register at www.aldec.com/dac2013 to attend a technical sessions led by Aldec’s top engineers from all over the world. I can’t stress enough how important it is to pre-register since these sessions do fill up quickly. You’ll also get a free t-shirt when you attend one of our sessions – we’ve designed some pretty cool ones to give away this year.
Aldec has also teamed up with Agilent to deliver a DAC Insight Presentation on Wireless Algorithm Validation Wednesday, June 5, 2013 from 2:00-4:00pm. Learn more.
