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 Aldec Design and Verification
Bill Jason
Bill Jason
Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for … More »

Aldec and Xilinx, Partnered for Success

July 8th, 2013 by Bill Jason

HW/SW Emulation and Functional Verification of Xilinx FPGAs

As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend “Smarter 2013”, Xilinx’ annual Technical Sales Conference.

Since Aldec is a Xilinx Alliance Member, we have been invited to showcase our solutions at their conference’s Partner Night. Working closely with key technology partnerships like Xilinx has long been the cornerstone to Aldec’s success. Our mutual customers have benefited from these alliances, the result of hard work, open communication and close interaction between our teams.

Most recently, we’ve been syncing with our counterparts at Xilinx to fulfill the verification requirements of the newest SoC designs, as Aldec provides EDA solutions at every stage of development. Users can leverage the latest Xilinx ISE and Vivado design suites to simulate and verify designs in Aldec Active-HDL and Riviera-PRO, or incorporate Aldec FPGA-based prototyping boards utilizing Virtex-7 FPGAs for hardware emulation and SoC prototyping.

As trends in FPGA architecture continue to provide hardware designers with larger capacities, embedded processors, and high speed interfaces, EDA vendors such as Aldec continue to work closely with Xilinx to make sure the verification requirements are maintained.

Here’s a closer look at what we’ll be sharing at this event:

Next-Generation FPGAs Utilized in Aldec HES

The Xilinx Virtex-7 utilizes Stacked Silicon Interconnect Technology, providing up to 2M logic cells, 70% lower power reduction, and 2.8 Tb/s total serial bandwidth.  With such a large logic density and high performance, the Virtex-7 is ideally suited for the SoC / ASIC prototyping and HW/SW Emulation space. Aldec utilizes the Virtex-7 FPGAs in its Hardware Emulation Solutions, a unified platform for Simulation Acceleration, Transaction-Level Emulation, HW/SW Co-verification, Software Validation, Virtual Modeling, and Prototyping.

Visit for more on Aldec HES.

Zynq SoC Verification with Aldec Riviera-PRO

The Xilinx Zynq SoC is the latest in Xilinx technology, utilizing a dual ARM Cortex-A9 processor with FPGA logic. This allows the development of software applications, drivers, or integrating operating systems with FPGA-based designs. The flexibility provided by the serial processing of the ARM Cortex-A9 and parallel processing of the FPGA fabric, allows developers to create system designs spanning multiple industries.  Aldec Riviera-PRO addresses verification needs of today’s cutting-edge FPGAs and SoC devices such as the Xilinx Zynq. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

For further reading, see our latest Xilinx-related App Notes: Compiling Xilinx™ Vivado Simulation Libraries for Riviera-PRO and Performing Functional Simulation of Xilinx™ Zynq BFM in Riviera-PRO.

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Categories: Emulation/Acceleration, Functional Verification, SoC and ASIC Prototyping

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