Archive for the ‘Functional Verification’ Category
Friday, January 10th, 2014
 When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
(more…)
Tags: Active-HDL, aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
No Comments »
Wednesday, December 11th, 2013
 Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.
 Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews. The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.
Our Commitment to the VHDL Community
When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Active-HDL, advanced verification platform, Aldec, aldec design rule checker, aldec dna, aldec simulators, alint, bitvis, do-254/ed-80 vhdl rule plug-ins, eda industry, embedded psl, FPGA Design, functional coverage, HDL, highest productivity to value ratio, ieee, ieee 1076-1993 Standard, ieee 1076-2002 vhdl standard, ieee 1076-2008 standard, ieee standard, ieee vhdl, intelligent testbench methodology, open source vhdl verification methodology, osvvm, psl embedded in vhdl, randomization, Riviera-PRO, simulation, source encryption, standards, starc vhdl, vector implementation of integer arithmetic, verification, VHDL, vhdl community, vhdl designs, vhdl testbench, vhpi interfacing to C/C++ code
No Comments »
Monday, November 25th, 2013
 COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.
To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: agilent, Aldec, co-simulation, co-simulation flow, co-simulation solution, comrate, debugging, digital blocks, hdl models, mixed-signal, model-based design, multirate design, Riviera-PRO, system-level environment, system-level simulation, systemvue, verification, verification of multirate systems with multiple digital blocks
No Comments »
Tuesday, September 24th, 2013
 Jim Lewis, VHDL Training Expert at SynthWorks (and founding member of OSVVM, which Aldec was an early adopter of) was kind enough to author a guest blog for Aldec. Here’s an excerpt:
After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received a great question, “Why Randomize?”
The easiest way to answer this is with an example. Let’s look at a FIFO test – test a FIFO, write to it, read from it, write to it and read from it simultaneously, fill it and see that additional writes are held off successfully, and empty it and see that additional reads are held off successfully.
Most certainly a FIFO can be tested using a directed test (just code, no randomization). The following simulation waveform shows diffcount (the number of words in the FIFO) for a directed test. The lowest value is empty. The highest is full. Using this, you can visually check off all of the required conditions and see that the FIFO is indeed tested.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, coverage, fifo test, functional coverage holes, intelligent coverage, os-vvm, osvvm-style constrained random, randomization, systemverilog, VHDL, vhdl testbench techniques
No Comments »
Monday, September 16th, 2013
 It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2), we at Aldec and Tanner EDA have received many inquiries from the field, conducted a number of evaluations, and deployed our analog/mixed-signal (AMS) design flow with our first mutual customers. In this article, I’ll share more the mixed-signal simulation methodology and highlight some of Verilog-AMS use cases that we have seen in the field.
Digital & Analog HDLs
The Verilog and VHDL languages were designed to handle discrete signals, where the number of possible signal values is limited (e.g. 1, 0, X, Z). Whereas Verilog-A was designed to handle continuous-time (analog) signals, that can take any value from a continuous range at any point.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, analog, co-simulation, digital, hiper simulation a/ms, mixed-level simulation, mixed-signal, mixed-signal design approach, Riviera-PRO, safety-critical, simulation-based verification, tanner eda, transistor-level implementation, verilog-ams simulators, vhdl languages
7 Comments »
Monday, August 12th, 2013
Fast Track to SystemVerilog for Verilog Users
The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.
Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!
(more…)
Tags: Aldec, design, design subset of systemverilog, fast track online trainings, simulation, system verilog, training, verification, verilog, VHDL
No Comments »
Wednesday, July 24th, 2013
 Breaking the Bottleneck of RTL Simulation
Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.
(more…)
Tags: acceleration, Aldec, asic gates, FPGA, fpga boards, fpga-based prototyping boards, hardware acceleration, Hardware Emulation, HDL, hdl simulation, hes design verification manager, HES-DVM, Riviera-PRO, rtl simulator, soc design, system-on-chip verification cycle
No Comments »
Monday, July 22nd, 2013
 To Accelerate DSP Design Development
If we’re being honest, human beings, especially engineers, are lazy. Let’s face it, most inventions ever made were created for the sole purpose of making our lives easier. The same goes for the manner in which we create our designs. In the not so distant past, engineers were drawing designs by hand on huge trace paper, placing them one below the other to form layers. This sounds like hard work to me! The lazy me would have wanted a smart (read: easy) solution to this process. Then along comes the EDA industry, which Aldec has been part of since 1984, making it much easier for us to do our designs.
Some might argue that EDA was born out not out of laziness, but in fact neccessity, due to increasing design complexity. True, it is impossible to imagine how the pencil and paper method could even work today. The point is it didn’t, and we now have automated the process to such an extent all you need do is enter some parameters in a tool wizard.
(more…)
Tags: accelerate dsp design development, Aldec, co-simulation, data analysis, data visualization, debugging, design, dsp algorithm, eda industry, edif cells, hdl code, hdl simulator, matlab, Riviera-PRO, simulink, verification, verilog modules, vhdl entities
No Comments »
Monday, July 8th, 2013
HW/SW Emulation and Functional Verification of Xilinx FPGAs
 As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend “Smarter 2013”, Xilinx’ annual Technical Sales Conference.
Since Aldec is a Xilinx Alliance Member, we have been invited to showcase our solutions at their conference’s Partner Night. Working closely with key technology partnerships like Xilinx has long been the cornerstone to Aldec’s success. Our mutual customers have benefited from these alliances, the result of hard work, open communication and close interaction between our teams.
Most recently, we’ve been syncing with our counterparts at Xilinx to fulfill the verification requirements of the newest SoC designs, as Aldec provides EDA solutions at every stage of development. Users can leverage the latest Xilinx ISE and Vivado design suites to simulate and verify designs in Aldec Active-HDL and Riviera-PRO, or incorporate Aldec FPGA-based prototyping boards utilizing Virtex-7 FPGAs for hardware emulation and SoC prototyping.
(more…)
Tags: FPGA, FPGA Simulation, Functional Verification, Hardware Emulation, Hardware-Assisted Verification, HES, Riviera-PRO, SoC, SoC and ASIC Prototyping, Virtex-7, Xilinx, Zynq
No Comments »
Monday, June 24th, 2013
 Productivity Boosting Features
Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and to help them use it more efficiently.
There are two main categories for HDL editors (1) general purpose text editors, and (2) integrated text editors. Both have their own pros and cons, and in the end it is for each engineer to decide which suits their needs.
The HDL editor built into Active-HDL falls under the second category of integrated text editors. It offers many basic features (syntax highlighting, templates, columns selection, code folding, auto-formatting) as well as semantic features (code navigation, on-the-fly error detector), and also offers seamless integration with the simulator and version control system. The HDL editor in Active-HDL can be used with VHDL, Verilog, SystemVerilog, SystemC, C/C++, PSL, OVA, Perl scripts and Tcl scripts.
(more…)
Tags: Active-HDL, auto-formatting, c/c++, code analysis, code browser, code folding, code navigation, code template, columns selection, creating hdl text modules, HDL, hdl editors, on-the-fly error detector, ova, perl scripts, psl, syntax highlighting, system verilog, systemc, Tcl scripts, templates, value probes, verilog, VHDL
No Comments »
|
When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
