Posts Tagged ‘Cadence’
Thursday, August 2nd, 2012
When it comes to wow factor, nothing outpaces the August 3rd announcement that Synopsys is going to acquire Taiwan-based SpringSoft. The announcement is astonishing for three reason:
1) Synopsys just announced the acquisition of Ciranova last week. True, the details of that deal were not released and Ciranova is not a ‘large’ company – still, two acquisitions by Synopsys in as many weeks is noteworthy.
2) SpringSoft is a publicly-traded company and therefore the details of the acquisition must be announced: Synopsys will be paying about $300 million for SpringSoft (net of cash acquired), which is a helluva lot of money …
3) … given that Synopsys has already executed another high-profile, high-priced acquisition of a publicly traded company earlier this year, buying Magma Design Automation for about $523 million (net of cash acquired).
Wednesday, August 1st, 2012
When Eric Filseth took over as CEO at Ciranova in September 2007, he was already a seasoned EDA veteran having clocked in an accumulated 17 years at Cadence at that point. Now here in 2012, Ciranova has just been acquired by Synopsys and it would seem Filseth’s organization has fulfilled the vision he articulated 5 long years ago.
Per Filseth in 2007: “The problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.
“There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day.
“Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed but in analog, people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and Ciranova is well positioned to take advantage of that opportunity.”
Thursday, July 26th, 2012
We’re coming up on almost four years, full on, since the momentous events of 15 October 2008 when the entire top executive team at Cadence exited stage left.
At the time, of course, the world was paying a shade less attention to EDA, and a shade more attention to a global crisis unfolding minute-by-minute featuring household concepts such as bankruptcy, subprime mortgages, and derivatives, and household names such as Lehman Brothers, AIG, Merrill Lynch, Bank of America, Goldman Sachs, Morgan Stanley, Washington Mutual, JPMorgan, Wachovia, CitiGroup, and the FDIC, to name a few.
Meanwhile, the folks who held CDNS in mid-October 2008 were holding shares that had lost almost 80% of their value over the previous 12 months, plummeting from $20+/share to around $4/share in that time frame.
The world may have been consumed by news of the larger global meltdown in October 2008, but various CDNS shareholders were sufficiently focused on the disaster at Cadence to precipitate upwards of a dozen class-action suits against the company in protest.
Thursday, July 19th, 2012
This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.
I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.
Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”
I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.
“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence], Jerome Cornet [STMicroelectronics], Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.
Wednesday, July 18th, 2012
To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.
If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.
Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.
Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.
And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.
Thursday, July 12th, 2012
It may be summertime, but the folks in the Verification world are clearly not taking any holidays.
This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!
Thursday, July 5th, 2012
The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?
Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …
… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.
This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?
Thursday, May 31st, 2012
If Silicon Valley is all about articulating and executing on a vision, then Santa Clara based Uniquify is all about Silicon Valley. The company has been in business since 2005, and since that time has worked to crystallize and clarify its vision and road map.
The vision is succinct and to the point: Make creating chips easier and faster, and with better results.
And from what I heard on a lengthy phone call today with Uniquify CEO Josh Lee, the company thinks they’ve nailed it, realizing that vision in three distinct ways. Per Lee, “Number one is design services. With us this is a different beast than in the usual sense in that we start from a spec or idea from our customer, and take it all the way to GDS.
“In the past, design services – which emerged in the mid-1990s when the industry moved from the ASIC to the COT model – were either dealing with logical design or phsycial design. At Uniquify, however, we are doing them both together. As a result, our core business is best described as ‘from spec to GDS’.
Wednesday, May 30th, 2012
Founded in 2000 in France, EVE has been a highly visible part of the EDA landscape for over a decade. In the week prior to the Design Automation Conference in San Francisco, I spoke by phone with Lauro Rizatti, General Manager and Marketing VP for EVA-USA, headquartered in Silicon Valley.
Lauro said that EVE is not releasing specific news at DAC because the company is launching the newest version of its ZeBu emulator in November 2012, the ZeBu-Server2 based on the Xilinx Virtex 6. Following that, EVE will be releasing the ZeBu-Server3 in mid-2014 based on the newest version of Xilinx Virtex 7. It’s not a coincidence that EVE’s hardware, built around ‘off the shelf’ FPGAs, enjoys a new release every two years.
Per Lauro: “Working with FPGAs, we don’t have to wait for internal, custom chip development to move forward. And because we use Xilinx, we ride their technology road map. Every 2 years they launch a new platform, and every 2 years so does Eve. We think we have a brilliant strategy, and the results can be seen in our earnings. We recognized $52 million revenue and $62 million in bookings over the last 12 months.”
Wednesday, May 16th, 2012
On May 1st, Joe Costello was standing in his office at Orb Networks on the 6th floor of a building in downtown Oakland. When we started our phone call, he said, “I’m looking down on Broadway and there’s a massive march out there. It’s crazy — wish I could send you the video!”
It was, of course, the May Day Occupy Oakland march, which seemed just about right for this long-planned interview.
Twenty years ago, Joe Costello was CEO at Cadence; today he’s President & CEO at Orb Networks, a company that’s “cranking away at cool stuff in the media space.” Twenty years ago, Joe Costello was the epicenter of EDA; today he’s roiling things up elsewhere in the technology ecosystem.
So first we talked about Joe’s present and future, and then we got around to EDA’s present and future and What Would Joe Do if he was back in the epicenter today.