Posts Tagged ‘Cadence’
Thursday, November 8th, 2012
It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.
Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”
He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”
All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.
Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”
Thursday, September 13th, 2012
Samsung Venture Investment Corp. has just put $4 million into Carbon Design Systems in conjunction with the debut of a new strategic partnership between the two companies.
Per the September 12th Press Release: “Funds from the strategic investment will be used as working capital and will support Carbon’s ongoing development of leading tools in the ESL design space, including its fast, accurate virtual prototypes. Initiatives will be undertaken to expand the reach of Carbon’s fast, accurate virtual prototypes.”
I spoke with Bill Neifert, Carbon’s founder, CTO and VP of Business Development on the day of the announcement. He was amazingly relaxed, a clear indication that the Samsung-Carbon partnership is a logical outcome of a long-term relationship between the organizations:
“Samsung been a heavy user of our tools for quite some time, and has been looking for ways to take even more advantage of that situation – to speed up product introductions, something that everyone’s trying to do in that marketplace.
“Today’s announcement is part of a Samsung initiative to advance their SoC design methodologies. They have both the resources and expertise today to innovate and are looking to us to help them with that. This is also a nice partnership for us, of course. It will help us share our methodology in a broader fashion.”
I asked if Samsung’s investment will jettison Carbon into an even better market position.
Bill said, “Yes, but this is a true partnership. It’s not just about money for Carbon, but about having additional access to Samsung’s time, expertise, and technology. Samsung wants to make better products, and enhancing our technology will also expand their customer base.”
Wednesday, August 15th, 2012
This week, Cadence announced availability of the 400-page Mixed-Signal Methodology Guide written by Jess Chen, Michael Henrie, Monte Mar, Mladen Nizic, et al, edited by EDA DesignLine’s Brian Baily.
Cadence says the book is targeted at both chip designers and CAD engineers, and “focuses on current and future advanced mixed-signal design challenges and solutions.” The company also says the book is “critically acclaimed and much anticipated,” which is a little confusing; if the book is much anticipated, how could it already be critically acclaimed?
Nonetheless, the availability of the book on Lulu.com – an on-demand self-publishing website – makes the text easy to purchase and reasonably priced: $69.00, marked down from $115 if you buy it by August 31st. The question is not one of price, however, but of usefulness: Where else are you going to get information on mixed-signal design if you want to get it out of a book?
If you go to Amazon, for instance, what can you find? Below is a small sampling of what’s currently available. Sorry for the tedious assignment, but if you scan through the contents of each book you’ll see there’s quite a bit of overlap, and there’s also quite a bit of differentiation. Looking at the first 4 selections on the list, and then comparing them to the 2012 Cadence publication, you may actually conclude that this new book by Chen et al is indeed bringing something very useful to the discussion of mixed-signal design, albeit with a focus on Cadence tools.
Thursday, August 2nd, 2012
When it comes to wow factor, nothing outpaces the August 3rd announcement that Synopsys is going to acquire Taiwan-based SpringSoft. The announcement is astonishing for three reason:
1) Synopsys just announced the acquisition of Ciranova last week. True, the details of that deal were not released and Ciranova is not a ‘large’ company – still, two acquisitions by Synopsys in as many weeks is noteworthy.
2) SpringSoft is a publicly-traded company and therefore the details of the acquisition must be announced: Synopsys will be paying about $300 million for SpringSoft (net of cash acquired), which is a helluva lot of money …
3) … given that Synopsys has already executed another high-profile, high-priced acquisition of a publicly traded company earlier this year, buying Magma Design Automation for about $523 million (net of cash acquired).
Wednesday, August 1st, 2012
When Eric Filseth took over as CEO at Ciranova in September 2007, he was already a seasoned EDA veteran having clocked in an accumulated 17 years at Cadence at that point. Now here in 2012, Ciranova has just been acquired by Synopsys and it would seem Filseth’s organization has fulfilled the vision he articulated 5 long years ago.
Per Filseth in 2007: “The problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.
“There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day.
“Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed but in analog, people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and Ciranova is well positioned to take advantage of that opportunity.”
Thursday, July 26th, 2012
We’re coming up on almost four years, full on, since the momentous events of 15 October 2008 when the entire top executive team at Cadence exited stage left.
At the time, of course, the world was paying a shade less attention to EDA, and a shade more attention to a global crisis unfolding minute-by-minute featuring household concepts such as bankruptcy, subprime mortgages, and derivatives, and household names such as Lehman Brothers, AIG, Merrill Lynch, Bank of America, Goldman Sachs, Morgan Stanley, Washington Mutual, JPMorgan, Wachovia, CitiGroup, and the FDIC, to name a few.
Meanwhile, the folks who held CDNS in mid-October 2008 were holding shares that had lost almost 80% of their value over the previous 12 months, plummeting from $20+/share to around $4/share in that time frame.
The world may have been consumed by news of the larger global meltdown in October 2008, but various CDNS shareholders were sufficiently focused on the disaster at Cadence to precipitate upwards of a dozen class-action suits against the company in protest.
Thursday, July 19th, 2012
This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.
I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.
Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”
I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.
“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence], Jerome Cornet [STMicroelectronics], Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.
Wednesday, July 18th, 2012
To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.
If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.
Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.
Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.
And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.
Thursday, July 12th, 2012
It may be summertime, but the folks in the Verification world are clearly not taking any holidays.
This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!