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Posts Tagged ‘Riviera-PRO’

The UVM Configuration Database

Tuesday, May 31st, 2016

blog_img_053116_01When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A database works much the same way, a collection of information that is stored and accessed on demand.

 

Take the UVM configuration database for example. It basically acts as a repository so that when the time comes, certain portions of the UVM testbench can be obtained from the database and used to build the structure.

 

When items are placed in the database with a set() method (uvm_config_db::set()), components in lower levels will call the get() method in order to obtain the necessary parts to build the verification framework.

 

Sharing an interface

 

If I were to ‘set’ an interface from my top level into the database while simultaneously giving it an identifying name, officially referred to as the ‘field name’, I could later use the field name to retrieve that interface in my driver to connect to the DUT by calling the get() method (uvm_config_db::get()).

 

 

Fig. 1) Setting the interface in the configuration database using an identifier ‘my_identifier’

 

 

Fig. 2) In order to connect a monitor or driver to the dut, the get() function will need to be called to access the interface in the respective build phase.

 

Setting up configurations

 

dac 2016If I wanted to change or modify my testbench structure, I could create a ‘configuration’. In my configuration, I could specify some rules as to what components I want my testbench to have. If I am designing a processor where I’ve already loaded up the memory with instructions, there’s no need to generate stimulus, therefore I could eliminate the driver and sequencer.

 

This is what UVM refers to as passive and active modes. Passive mode is where only a monitor exists to observe data and active mode is where a driver and sequencer are needed to generate stimulus. Placing certain variables in the configuration database can help to determine whether the testbench is setup as passive or active.

 

In order to declare the testbench as passive or active, a configuration object is created. The built in uvm_active_passive_enum data type is used to indicate whether the testbench is UVM_ACTIVE or UVM_PASSIVE.

 

 

Fig. 3) An example configuration

 

For the rest of this article, visit the Aldec Design and Verification Blog.

U.V.M. Spells Relief

Friday, December 4th, 2015

blog_120215Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.

 

So what is UVM?

UVM stands for universal verification methodology and is based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.

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Helping FPGA Designers get started with UVM

Tuesday, September 8th, 2015
Doulos has partnered with Aldec to deliver this Friday’s webinar, ‘Easier UVM: Helping FPGA Designers Get Started with UVM’ . Presented by Doulos CTO, John Aynsley, the 1 hour webinar includes live Q&A so it’s a great opportunity to find out how Easier UVM can work for you. The webinar includes examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™.

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How Can Verification IPs Help the SoC Testing Process?

Monday, April 20th, 2015

 

How to use VIPs In Practice

figure 0
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.

Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.

Figure1 typical verification process
Figure 1. Typical verification process

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Scaling the “Internet of Things”

Wednesday, January 21st, 2015

Internet-of-thingsHappy New Year!

January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.

The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).

Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.

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Simulate Smarter than a Secret Agent

Thursday, March 13th, 2014

In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools and how to use them most efficiently.

Sure, that would probably eliminate all of the plot twists that make for a great movie, but when it comes to real life – I don’t care for plot twists. What about you? If you were a secret agent given these tools to keep you out of trouble or even save your life – would you take the time to learn about all of the features?

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It’s no accident that Aldec offers the best VHDL-2008 support

Wednesday, December 11th, 2013

Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.

Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews.  The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.

Our Commitment to the VHDL Community

When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.

For the rest of this article, visit the Aldec Design and Verification Blog.

Effective Communication is Key in Relationships… and ESL Design!

Monday, November 25th, 2013

COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.

To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):

For the rest of this article, visit the Aldec Design and Verification Blog.

 

Verilog-AMS & Multi-Level Simulation

Monday, September 16th, 2013

It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2), we at Aldec and Tanner EDA have received many inquiries from the field, conducted a number of evaluations, and deployed our analog/mixed-signal (AMS) design flow with our first mutual customers. In this article, I’ll share more the mixed-signal simulation methodology and highlight some of Verilog-AMS use cases that we have seen in the field.

Digital & Analog HDLs

The Verilog and VHDL languages were designed to handle discrete signals, where the number of possible signal values is limited (e.g. 1, 0, X, Z). Whereas Verilog-A was designed to handle continuous-time (analog) signals, that can take any value from a continuous range at any point.

For the rest of this article, visit the Aldec Design and Verification Blog.

Leverage Hardware Acceleration for Faster Simulation

Wednesday, July 24th, 2013

Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.

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CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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