Aldec Design and Verification
Henry provides support and guidance to Aldec customers as an Applications Engineer. Specializing in Active-HDL™ and Riviera-PRO™, he is well versed in Aldec’s industry leading FPGA design and simulation tools. His diverse knowledge from hardware description languages to functional … More »
SystemVerilog Functional Coverage in a Nutshell
March 15th, 2018 by Henry Chan
Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that have occurred on your signals.
Consider an 8-bit address signal, paddr, and a 32-bit data signal, pwdata. Assigning a coverpoint to each signal will direct your simulator to track these signals during simulation and record the number of hits. For each coverpoint, bins can be created to organize the possible signal values into meaningful categories. Finally, a covergroup is used to encapsulate it all and is instantiated using the new() constructor. Associating the covergroup with a clock event is also a good way to trigger the coverage sampling.
Figure 1: Example Functional Coverage Syntax
Each covergroup contains options for configuration which allows customization. The example shown in Figure 1 uses options which determine the number of bins that are created for the pwdata signal and whether the covergroup is static across all instances or if there should be a separate covergroup for each instance in which the new() constructor is called. Other options allow you to change the weighting structure for your covergroups and specify the target coverage goal percentage and required number of hits for each bin; plus other options.
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