Posts Tagged ‘TSMC’
Thursday, October 5th, 2017
Taking guidance from their website, Silicon Valley based Helic provides “EDA software that mitigates the risk of electromagnetic crosstalk in high-speed and low-power SOC designs.”
The company’s products include VeloceRF, an inductive device compiler and modeling tool which provides DRC clean devices for geometries as low as 10 nanometers; RaptorX, a pre-LVS electromagnetic modeling tool; and Exalto, a post-LVS RLCk extraction tool that captures unknown crosstalk including electrical, magnetic, and substrate coupling.
In other words, Helic is a company with a very technical portfolio of products, which can be daunting if one wants to speak with the leadership.
But that was not the real problem posed during my recent conversation with Helic President and CEO Yorgos Koutsoyannopoulos. The last time the two of us spoke, he made a bet I could not pronounce his name correctly. I won that bet, although Koutsoyannopoulos then proceeded to pronounce my name correctly as well, something that fewer than 1-in-10 in EDA can actually do.
Alas during our recent conversation – the one documented below – the Helic CEO could still pronounce my last name correctly, but I stumbled over his.
In my defense, Koutsoyannopoulus has 16 letters, 56% of which are vowels, and I hadn’t practiced in advance of our call. My last name only has 8 letters, but 63% of them are vowels, so mine is actually more difficult to pronounce. I should not have let Yorgos best me in this contest. Next time I will be better prepared.
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Tags: Ansys, Bob Smith, electromagnetic crosstalk, ESD Alliance, finFET, Helic, TSMC, Yorgos Koutsoyannopoulus
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Thursday, September 28th, 2017
Vic Kulkarni is well-known in the EDA community as co-Founder, CEO and President of Sequence Design from 1995 until the company merged with Apache in 2009, which in turn was acquired by ANSYS in 2011. Kulkarni is now VP and Chief Strategist in the Office of CTO for the Semiconductor Business Unit at ANSYS.
There is little Kulkarni has not seen in his 30+ years in Silicon Valley. Although our conversation here mostly highlights current successes at ANSYS, it’s clear he continues to be wildly enthused about the broader promises of technology and the exciting efforts underway to create tools and strategies to bring those promises to fruition. Vik Kulkarni’s enthusiasm is the kind of thing that continues to make this industry so vibrant, and makes careers herein appealing for the next generation of engineers.
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Tags: Aart de Geus, Ansys, Apache, ARM, Bollywood, Cadence, DAC, ESD Alliance, John Lee, Lip-bu Tan, Mentor Graphics, Moore's Law, More than Moore, NVIDIA, Sequence Design, Synopsys, TSMC, Vik Kulkarni, Wally Rhines
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Thursday, August 31st, 2017
Amit Gupta is the quintessential entrepreneur in EDA. Even as he was graduating with degrees in EE and CS from University of Saskatchewan, he was co-founding Analog Design Automation, targeted at those who need tools to automate analog chip design. That was in 1999. The company was sold to Synopsys in 2004, and then Gupta co-founded Solido Design Automation in 2005.
This week, I had a chance to speak at length with Amit Gupta. The last time we conversed, it was at the January 2017 Kaufman Award dinner for Dr. Andres Strojwas in San Jose. That evening, Gupta was enthused about Solido’s access to high-quality engineering talent in Canada, and argued that the cost of living and quality of life in Saskatoon, where Solido is headquartered, more than compensate for any sense that Silicon Valley is the epicenter of the industry. His enthusiasm has only grown since that time.
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Tags: Amit Gupta, Analog Design Automation, Deloitte, Design Automation Conference, E3 Data Science, Eric Hall, ESD Alliance, finFET, GlobalFoundries, Gloria Nichols, Jeff Dyck, Mark Gilbert, NVIDIA, Qualcomm, Samsung, Saskatoon, SOI, Solido Design Automation, Sorin Dobre, Synopsys, Ting Ku, TSMC, UX design
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Thursday, March 23rd, 2017
Something historic and poignant is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.
The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.
The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.
Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.
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Tags: Aart de Geus, Abu Dhabi, ARM, Brexit, Cadence, Charles Crocker, China, Collis P. Huntington, Ed Sperling, EDA, EDA 360, Egypt, ESD Allicance, Germany, GlobalFoundries, India, Japan, Leland Stanford, Lip-bu Tan, Mark Hopkins, Mentor Graphics, Pakistan, Russia, Saudia Arabia, Semiconductor Engineering, Siemens, Simon Segars, SoftBank, Synopsys, Taiwan, TSMC, U.S., UK, Wally Rhines
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Thursday, March 24th, 2016
To speak with Herb Reiter about the rationale for multi-die packaging is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.
Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.
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Tags: Asim Salim, autonomous driving, Cliff Hou, Dusan Petranovic, eda 2 asic, EDPS, Ford, Gary Smith, Google, Herb Reiter, ITRS, Ivor Barber, Multi-die packaging, Paul Silvestri, Riko Radojcic, TSMC
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Thursday, July 30th, 2015
It’s been 10 years since I first explained why TSMC should buy Cadence. Now a decade on, many things have changed in the world and many have not.
Among the things that have not changed? TSMC still should buy Cadence.
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Means …
First of all, let’s look at the numbers (per Yahoo Financials re: 2014):
* Taiwan Semiconductor Manufacturing Co. Ltd.
Employees: 43,500
Market Cap: $166.44 billion
Revenue: $27.31 billion
Operating margin: 39.26%
Net income: $9.70 billion
Total Cash: $16.61 billion on $7.40 billion in debt
* Cadence Design Systems Inc.
Employees: 6,100
Market Cap: $6.14 billion
Revenue: $1.61 billion
Operating margin: 11.23%
Net income: $161.1 million
* Conclusion
TSMC has got the means to buy Cadence.
By a long shot.
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Tags: Cadence, Lip-bu Tan, SpringSoft, Synopsys, Taiwan, TSMC
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Thursday, June 11th, 2015
It’s always hard to capture the spirit of any particular trade show/tech conference when it’s as large as DAC. So here’s just a small sample of the rumors and realities being bandied about at Moscone Center this week in San Francisco.
* Rumor: The Exhibit Hall ran until 7 pm on Wednesday night, so if you wanted to see the bagpipes close out the show, you could see it if you arrived at the Cadence booth by 6:45 pm.
* Reality: The Exhibit Hall closed at 6 pm on Wednesday, not 7 pm as on Monday and Tuesday. The bagpipes closed out the show, but at 6 pm, not 7 pm. Those who missed it were very, very sad.
* Rumor: DAC’s Exhibition Hall has shrunk so much over the last few years, it’s no longer going to be housed at Moscone Center. After next year’s DAC 2016 in Austin, the show’s headed to the San Jose Convention Center in 2017.
* Reality: Moscone Center is being renovated over the next several years, so DAC’s going to be in Austin in 2016, in Austin in 2017, and (probably) back in San Francisco in 2018.
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Tags: Cadence, CEDA, Common Platform, DAC, Design Automation Conference, GlobalFoundries, Imagination Technologies, L.A. Clippers, Mentor Graphics, MIPS, Moscone Center, San Jose Convention Center, SMIC, Synopsys, TSMC
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Thursday, October 30th, 2014
Tanner EDA is based in Monrovia, California, which already tells you something about the company. They don’t play by the expected rules in EDA, they’re not based in Silicon Valley, they’re independent-minded, customer-centric, and have a long-time commitment to interoperability and straight-forward messaging.
When I spoke by phone this week with Tanner President Greg Lebsack, I suggested that Tanner is the Madison Bumgarner of EDA – steady, delivering without fanfare, successful and consistently attributing that success to team and hard work, while also expressing respect for the competition in the league.
Lebsack chuckled at the comparison and suggested an L.A.-based pitcher would be a more appropriate Tanner totem, one that wouldn’t get him in hot water with friends and family, but if I couldn’t see past Bumgarner he would reluctantly accept the compliment.
He added, “From the founding of Tanner, we have been a company built by engineers for engineers and taking great pride in our products. Being a small company without the marketing budget of the big companies, it’s true we are a well-kept secret in EDA, but that is changing with more and more people taking notice of us.”
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Tags: Cadence, Europractice, Greg Lebsack, Imec, iPDKs, Nicolas Williams, ON Semiconductor, OpenAccess, PDKs, Tanner EDA, TowerJazz, TSMC, X-Fab
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Wednesday, July 16th, 2014
Despite its ethereal-sounding name, Silicon Cloud International is a company grounded in the reality of chip design, particularly for an important international demographic, professors and students. Mojy Chian is CEO of the Singapore-based SCI. We spoke recently by phone.
Chian started by defining the cloud. “The concept of the cloud is straightforward. It means remote computing, so if you are not using your local machine, you are using the cloud. There are a lot of applications in the cloud, including eCommerce, Facebook, cloud storage, and remote collaboration based in the cloud.
“Certainly, usage of the cloud has taken off in recent years, but remember there are several different types of clouds. In contrast to private cloud computing, public cloud computing means accessing machines [owned by other companies such as Amazon], where you can actually go and use their machines.”
Our conversation being specific to chip design, I asked Chian to comment on widespread industry concerns regarding security when working in the public cloud. Companies are oft-times reluctant to compute and/or store their designs in the public cloud for fear of losing their precious data to hackers and pirates.
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Tags: Cadence, cloud computing, EDA, GlobalFoundries, Mojy Chian, MOSIS, private cloud, public cloud, Silicon Cloud International, SRC, Synopsys, TSMC
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