Posts Tagged ‘Intel’
Wednesday, April 22nd, 2015
If there’s something missing in your personal or professional knowledge of Moore’s Law, you should have spent 5 hours at the Computer History Museum in Mountain View on April 17, 2015, although even then you might not have learned anything new. For people in technology, seriously, what more is there to know?
The ‘law’, penned by Gordon Moore and published in an Electronics article on April 19, 1965, was based on his many years’ experience in the nascent-to-ferocious semiconductor industry, and has since been interpreted, re-interpreted, mis-interpreted, and zealously lionized – both the law and the man – over the last 50 years. Which brings us back to April 17th and the 3-part program at the CHM.
(more…)
Tags: Arnold Thackray, Cal Tech, Carver Mead, Computer History Museum, David Brock, Fairchild, Gordon Moore, Intel, John Hollar, Linus Pauling, Moore's Law, San Jose State University, Silicon Valley, The Gordon & Betty Moore Foundation, U.C. Berkeley, William Davidow, William Shockley
No Comments »
Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
(more…)
Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
No Comments »
Thursday, October 16th, 2014
There are three types of Italian genius. Leonardo da Vinci characterized one with his brilliant problem solving, creative innovations in the arts and sciences, diverse dabblings that often left completion dates for commissioned projects as sfumato as his oils, and aggressive self-promotion. An apocryphal testimonial to this last: When he finished the Mona Lisa in the early 1500s, he invited friends and foe alike into his studio to show off what he assured them would be the Next Big Thing. Humility was not in Leonardo’s toolkit.
Born in 1475, Michelangelo Buonarroti exemplified a second type of Italian genius. Intense, focused, gifted with extraordinary talents in the visual arts and architecture, and rumored to be so impassioned by his work as to go weeks on end without sleep, his talent was such that monumental commissions were forced upon him by the political and religious powers of the day, although he argued bitterly against the scale of such assignments. He became increasingly cantankerous with age, and in angry response to criticism of one commission in particular, famously painted himself into his vast Last Judgment as a flayed skin victimized by his patrons. Charm and affability were not in Michelangelo’s toolkit.
Fast forward five centuries and find now a completely different type of Italian genius. Shaped by mid-20th century forces in technology, and brought to full fruition in the fertile fields of Silicon Valley, Lucio Lanza exemplifies a third class in the taxonomy, one that encompasses the upsides of those 16th century icons – intelligence, creativity, a passion for innovation and work, a sense of history – without the downsides – egomania, rough irritability, inability to finish a project, or avoid a project too big to handle.
In the wake of two High-Renaissance Florentians, it took one High-Tech Milanese to fill out the taxonomy of Italian genius. Here in the 21st century, Lucio Lanza is in a modern class of his own.
(more…)
Tags: Cisco, Crescendo Communications, Dante Alighieri, Divine Comedy, EDAC, Gutenberg, Intel, Lanza techVentures, Ledonardo da Vinci, Lucio Lanza, Michelangelo Buonarroti, Phil Kaufman, Phil Kaufman Award
No Comments »
Thursday, September 25th, 2014
Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.
Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.
He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”
(more…)
Tags: Accellera, Cadence, CEDA, Dennis Brophy, DVCon, IEEE Standards, Intel, Jill Jacobs, Karen Pieper, Mentor Graphics, Shishpal Rawat, Synopsys, System Verilog AMS standard, SystemC, UPF, UVM, Verilog
No Comments »
Tuesday, June 10th, 2014
UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’
In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.
Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”
It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.
Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.
(more…)
Tags: Ajat Hukkoo, Ashu Bakhle, Broadcom, DAC 2014, GlobalFoundries, Hong Hao, Intel, Luigi Capodieci, Samsung, Sandip Kundu, University of Massachusetts Amherst
No Comments »
Thursday, January 23rd, 2014
Long, long ago in a galaxy far, far away the EDA Empire began and quickly coalesced into several big players and a band of plucky startups constantly attempting to compete and stay viable.
Back in that halcyon era, Rick Carlson and Dave Millman decided to get those startups to pull as one, to try to keep the industry open and progressing, to protect the EDA industry as a place where new ideas could see the light of day and offerings from small companies could compete on a level playing field against those from the big players.
To do that, Rick and Dave came up with the idea for a consortium of Independent Design Automation Companies, IDAC, and put out the word to like-minded colleagues that this new group would benefit everybody. Creating IDAC proved more difficult than they had hoped, so letting pragmatism rule the day they approached Joe Costello for help, then CEO of Cadence, even though that meant working with one of the ‘big guys’ and hence, EDAC came to fruition.
To hear the rest of the story per Rick, recounted in a phone call in December, click here.
To hear the story recounted by Joe Costello, read below. I spoke with both Joe and Rick together on a conference call in mid-January.
****************
Revolution from within …
Joe began: “Rick told me he’s concerned that in his recent conversation with you about the history of EDAC, he may have sounded too harsh. I said that’s not possible, because the truth about the industry is quite harsh. Just thinking about it makes my blood boil.
(more…)
Tags: all-you-can-eat EDA, Broadcom, Cadence, Dave Millman, EDAC, EDAC Interoperability Lab, IDAC, Intel, Joe Costello, Mentor Graphics, Qualcomm, Rick Carlson, Samsung, Synopsys
2 Comments »
Thursday, September 26th, 2013
A Professor, a Sage, and a Guru walked into a bar. Brian the Bartender, greeted them: “What’ll it be, boys?”
The Professor said, “We need some help, Brian, settling an argument.”
“No problema,” Brian the Bartender said. “I’ve got an answer for everything.”
“Well,” the Professor said, “I think ESL’s not going to happen in our lifetime, but the Guru here says it’s just around the corner now that he and his have finally got all the pieces of the flow in place.”
Brian the Bartender laughed, “Yeah, the Guru’s been saying that since the dawn of mankind!”
“Exactly,” the Professor said.
Again Brian the Bartender laughed, “Guru, can you defend yourself? And don’t even think about plunking your wordy White Paper down on the bar. This is a public house, not a public library.”
(more…)
Tags: Apache, ARM, Atrenta, Cadence, Cadence System-to-Silicon Verification Summit, Calypto, DOCEA, Duolog, ESL, Forte, Green Hills, Imperas, Intel, Jasper, MathWorks, Mentor Graphics, NVIDIA, Oasys, OneSpin, Real Intent, Synopsys, Verification, Wind River
1 Comment »
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
****************
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
(more…)
Tags: 2.5/3D ICs, AMD, Amkor, Chenming Hu, eda2asic, Elpida, FDSOI, finFET, Herb Reiter, Hybrid Memory Cube, Hynix, IBM, Intel, Micron, partially-depleted SOI, Samsung, SanDisk, Soitec, STMicro, Tezzaron, Toshiba, TSMC, Xilinx
No Comments »
Thursday, April 4th, 2013
Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.
Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.
(more…)
Tags: Adapt-IP, Alcatel-Lucent, Aparna Dey, ARM, Brandon Wang, Cadence, Camille Kokosaki, Dan Nenni, Docea Power, Don MacMillen, Dusan Petranovic, E-System Design, eda2asic, EDPS 2013, Frank Schirrmeister, Gary Smith, Gene Jakubowski, Gene Matter, Gregory Wright, Guy Bois, Herb Reiter, Intel, Ivo Bolsens, James Colgan, John Heilein, John Swan, Kiron Pai, Luigi Capodieci GlobalFoundries, Mentor Graphics, Michael McNamara, Micron, Mike Black, Namraj Nandra, Naresh Sehgal, Net App, Nimbic, Oracle, Raymond Leune, Rob Aitken, SemiWiki, Space Codesign, Srinivas Nori, Srinivasa Banna, Synopsys, Tom Dillinger, Tom Quan, TSMC, Xilinx, Xuropa
No Comments »
Thursday, December 13th, 2012
When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
(more…)
Tags: Asen Asenov, bulk CMOS, FDSOI, FinFETs, GlobalFoundries, GSS, IEDM, Intel, STMicro, University of Glasgow
No Comments »
|
