Posts Tagged ‘SoC verification’
Wednesday, February 10th, 2016
Regular readers of The Breker Trekker know that we like to preview, review, and dissect technical conferences and trade shows that are of interest to verification engineers. Perhaps the conference we’ve covered the most has been the annual Design and Verification Conference and Exhibition (DVCon) in San Jose. As far as we know, this is the biggest event anywhere focused on digital and system design and verification, a nice complement to the analog-ish DesignCon.
As a matter of fact, DVCon has become so successful that there are now regional conferences in India and Europe in addition to the U.S. show. We’ve strongly supported DVCon India, including serving for all three years on the Promotions Committee, and have participated in DVCon Europe as well. But those are a bit in the future; DVCon (U.S.) 2016 is coming up in a just a few weeks. The program is online now, so we thought we’d review it and suggest some sessions of possible interest.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 3rd, 2016
For more than four years now, Breker has branded itself as “The SoC Verification Company” and many people acknowledge our expertise in this domain. As we have discussed before on The Breker Trekker, our initial products focused on generating purely transactional tests for a simulation testbench, usually compliant with the Accellera Universal Verification Methodology (UVM) standard. When we extended our products to generate C code that runs on the embedded processors found within SoCs, we delivered on our “tagline” promise.
Since our early focus on simulating an SoC, we have expanded our technology and our product line to generate C test cases that run on embedded processors in emulation, FPGA prototypes, and actual silicon in the bring-up lab. In talking about what we do, we struggle to choose between “SoC” and “system” since for many of our customers the terms are synonymous. But we also have users verifying multi-SoC systems, and today we’d like to address that topic.
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Tags: application, Breker, bring-up lab, cache coherency, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, January 27th, 2016
Some of the highest readership here at The Breker Trekker happens when we post articles about the state of the semiconductor industry or EDA industry. It’s been a while since we looked inward at our own industry, but we have had a series of very popular posts about the ongoing changes in the semiconductor market, including the “merger mania” of the last few years. Although not all closed, in 2015 alone there were several dozen offers totaling well over US$150B.
Since semiconductor vendors are the main customers for EDA, with their customers the remainder of our market, we track both industries very closely. In last week’s post, we looked what the ongoing merger and acquisition (M&A) activity means for Silicon Valley. Our friend Graham Bell at Real Intent added a comment wondering about the impact of this M&A on the EDA industry. Today’s post contains some of our thoughts on this matter.
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Tags: acquisition, Breker, chip, Cypress, EDA, functional verification, IC Insights, Intel, Internet of Things, IoT, M&A, merger, semiconductor, Silicon Valley, SoC, SoC verification, Top 20
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Wednesday, January 20th, 2016
As someone who has lived in the heart of Silicon Valley for more than 30 years, I’m used to the regular cries that we’re losing our innovative edge. Every few years something happens to cast some doubt on our future: a stock market crash, a major company moving elsewhere, or a lot of press about some new Silicon Forest/Glen/Mountain/Prairie/Island/Whatever trying to beat us at our own game.
Sure, we face plenty of challenges. A recent article on SemiWiki painted a rather cautionary view of today’s Silicon Valley. But there’s good news too. Silicon “Valley” has grown to include San Francisco and much of the Bay area, with corresponding growth in technology employment and impact. Today, I’d like to springboard from a recent post on semiconductor mergers and acquisitions to consider one particular aspect of the current role of Silicon Valley.
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Tags: acquisition, Breker, chip, Cypress, EDA, functional verification, IC Insights, Intel, Internet of Things, IoT, M&A, merger, semiconductor, Silicon Valley, SoC, SoC verification, Top 20
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Tuesday, January 12th, 2016
Last week the International Consumer Electronics Show returned to Las Vegas, where it has been a major event for nearly 40 years. Nearly everyone calls this show CES, to the extent that its home page doesn’t even tell you what the acronym means anymore. So CES it is, one of the largest and best-known technology-oriented conferences in the world. Its sheer size makes it a test of stamina for exhibitors and visitors alike.
When people think of CES, they think of wandering the aisles and being overwhelmed by all the cool products on display. From massive HDTV screens down to the smallest Internet of Things (IoT) devices, this show appears to have it all. It seems to me, however, that CES has evolved into an event that’s almost as much about the underlying silicon as it is above the consumer-oriented end products. I’d like to explore that idea in today’s post.
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Tags: Breker, Broadcom, CES, Consumer Electronics Show, Cypress, EDA, EZchip, functional verification, Intel, Internet of Things, IoT, Marvell, MaxLinear, Omnivision, Qualcomm, semiconductor, Sigma Designs, SoC, SoC verification, system-on-chip, Texas Instruments, TI, Toshiba
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Wednesday, January 6th, 2016
It’s been more than a year since we presented the Breker view of system coverage in detail, so it’s time to revisit the topic. We first defined the notion of system coverage as measuring which realistic, system-level application scenarios have been exercised using the existing test cases. We then demonstrated how our graph-based scenario models are ideally suited to capture system coverage metrics and fine-tune them using graph constraints if needed.
More recently, we noted that the term “use cases” has become more widespread and introduced the example of a digital camera SoC to show the types of use cases that should be exercised. The measurement for this exercise is also system coverage, so the bottom line is that all these terms are really talking about the same thing. Using a regular expression, we might say:
[application|realistic] (scenario|use-case) coverage = system coverage
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, node coverage, path coverage, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, system coverage, test case generator, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, December 30th, 2015
It’s becoming somewhat of a tradition here on The Breker Trekker blog to close each year with a list of gifts available from us to verification engineers. We started the series two years ago with an initial list focusing on our core benefits of automatic test case generation, system coverage, and reuse both vertically (IP to system) and horizontally (simulation to silicon). Last year’s post offered five more gifts reflecting additional products and new features added to our overall solution:
#5: Easier sequence specification in UVM testbenches.
#4: Faster coverage closure in UVM testbenches.
#3: Integration of system coverage with other coverage metrics.
#2: Debug of automatic test cases using standard tools.
#1: A fully automated solution for cache coherency verification.
Every one of the ten gifts from 2013 and 2014 is still available today for our customers. In addition, we have continued to evolve our Trek family of products and to deploy it on ever more challenging SoC verification projects. Without further ado, here is our all-new list of holiday gifts for the verification engineer in 2015:
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Tags: acceleration, Accellera, Breker, coherency, coverage, EDA, emulation, FPGA prototyping, functional verification, graph, level shifters, low power, platforms, portable stimulus, power domains, PSWG, reuse, scenario model, silicon, simulation, SoC, SoC verification, system coverage, test generation, TrekApp, TrekSoC, TrekSoC-Si, TrekUVM, use cases, uvm, verification IP, VIP, virtual
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Tuesday, December 22nd, 2015
In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.
This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.
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Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, portable stimulus, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator
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Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
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Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
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Thursday, December 10th, 2015
The past two weeks, we’ve been having a bit of fun playing alchemist and letting readers in on some of the deep, dark secrets of graph-based verification technology. This week, we conclude the series by showing some additional capabilities for our scenario models that are easy to control and view in a graph visualization. Our point is, of course, that graphs are a natural way to represent data flow and verification intent with no advanced degrees from MIT, IIT, or Hogwarts required.
As a quick reminder, graph-based scenario models begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Breker’s Trek family can traverse the graph from left to right, randomizing selections to automatically generate test cases tailored to run in any target platform. Today, we continue using our example of a scenario model to verify that an automobile can move forward or stop.
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Tags: Accellera, Breker, constraints, cross-coverage, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, system-level coverage, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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