The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
A Preview of the Upcoming DVCon in San Jose
February 10th, 2016 by Tom Anderson, VP of Marketing
Regular readers of The Breker Trekker know that we like to preview, review, and dissect technical conferences and trade shows that are of interest to verification engineers. Perhaps the conference we’ve covered the most has been the annual Design and Verification Conference and Exhibition (DVCon) in San Jose. As far as we know, this is the biggest event anywhere focused on digital and system design and verification, a nice complement to the analog-ish DesignCon.
As a matter of fact, DVCon has become so successful that there are now regional conferences in India and Europe in addition to the U.S. show. We’ve strongly supported DVCon India, including serving for all three years on the Promotions Committee, and have participated in DVCon Europe as well. But those are a bit in the future; DVCon (U.S.) 2016 is coming up in a just a few weeks. The program is online now, so we thought we’d review it and suggest some sessions of possible interest.
As usual, the conference portion spans four days (Monday, February 29 through Thursday, March 3), with the two days in the middle also including a vendor exhibition. Monday is devoted to tutorials, including one from the Accellera SystemC Synthesis Working Group (SSWG). Of course, we’re big believers in C/C++ for verification and our tools also work well at verifying designs written in SystemC as a higher-level alternative to RTL.
Speaking of Accellera Systems Initiative, the standards group is sponsoring a lunch that will include an update from the Portable Stimulus Working Group (PSWG). As you surely know, Breker is one of the leaders of PSWG and we are working very hard to ensure that the upcoming standard for graph-based scenario models will enable all of the capabilities our customers have come to expect. There is also a short preview of the exhibits Monday evening, and of course Breker will be there.
Tuesday’s technical program is a typically rich and diverse one for DVCon. Topics include checking clock domain crossings, modeling analog systems, verifying low-power intent, programming in SystemVerilog, and using in-circuit emulation (ICE) effectively. But we already know the best talk of the day: “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session, co-authored by Breker and Cavium.
We hinted in last week’s post that this talk would describe “generating test cases for a multi-SoC configuration with well over 100 cores” and so it will. As you can see from their Web site, Cavium develops some of the biggest chips in the world, including data center and cloud processors with 48 ARM cores. We’re proud to say that we played a role in the verification of these designs, especially cache coherency, and are grateful to Cavium for allowing us to discuss their project.
Breker is back on the technical program Wednesday morning, as our founder CEO Adnan Hamid participates in the “Redefining ESL” panel 8:30-9:30 a.m. There are plenty of other interesting topics to be presented over the course of the day, including analog/mixed-signal (AMS) verification, regression test management, assertions and formal analysis, and a half-dozen talks on various aspects of the Universal Verification Methodology (UVM).
In addition to the preview on Monday evening 5:00-7:00 p.m., the exhibits will be open on both Tuesday and Wednesday 2:30-6:00 p.m. As always, we will have our best technical experts there to engage in lively discussions about your verification challenges, Breker’s products, and any possible alignment between the two. Finally, Thursday is devoted to more tutorials, including multiple topics by each of the “Big 3” EDA vendors and an intriguing session on “Solving the Next Big SoC Challenges…” by Altera and S2C.
We look forward to meeting you at our booth during the exhibition hours. If you’d like to schedule a particular time or request that an expert be available for a particular topic, just let us know. If you will be attending the technical conference as well, please be sure to listen to both our Tueasday talk on the Cavium project and the Wednesday ESL panel. Both will be don’t-miss sessions. Thanks for reading, and we’ll see you very soon at DVCon 2016.
The truth is out there … sometimes it’s in a blog.
Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm